Acceleration of input/output (I/O) communication through...

Electrical computers and digital processing systems: memory – Address formation – Address mapping

Reexamination Certificate

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Reexamination Certificate

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06976148

ABSTRACT:
An I/O communication adapter receives from a processor core an I/O command referencing an effective address within an effective address space of the processor core that identifies a storage location. In response to receipt of the I/O command, the I/O communication adapter translates the effective address into a real address by reference to a translation data structure. The I/O communication adapter then accesses the storage location utilizing the real address to perform an I/O data transfer specified by the I/O command.

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U.S. Appl. No. 10/339,723; filed Jan. 9, 2003; by Ravi Kumar Arimilli, et al.; For: High Speed Virtual Instruction Execution Mechanism.
U.S. Appl. No. 10/339,724; filed Jan. 9, 2003; by Ravi Kumar Arimilli, et al.; For: Data Processing System Providing Hardware Acceleration of Input/Output (I/O) Communication.

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