Electronic digital logic circuitry – Clocking or synchronizing of logic stages or gates
Reexamination Certificate
2006-08-11
2008-03-25
Barnie, Rexford (Department: 2819)
Electronic digital logic circuitry
Clocking or synchronizing of logic stages or gates
C326S098000, C326S121000, C327S201000
Reexamination Certificate
active
07348806
ABSTRACT:
A non-inverting dynamic register includes a domino stage, a mux, and an output stage. The domino stage evaluates a logic function based on at least one input data signal and a pulsed clock signal, and opens an evaluation window when the pulsed clock signal goes high, and pulls a pre-charged node low if it evaluates, and keeps the pre-charged node high if it fails to evaluate. The mux pulls a feedback node low if the pre-charged node goes low during the evaluation window, and pulls the feedback node high if the pre-charged node is high during the evaluation window. The output stage is coupled to the pre-charged node and the feedback node. The output stage provides an output signal based on states of the pre-charged and the feedback nodes.
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Bertram Raymond A.
Lundberg James R.
Barnie Rexford
Crawford Jason
Huffman James W.
Huffman Richard K.
Via Technologies Inc.
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