Accelerated life test of MRAM cells

Details Accelerated life test of MRAM cells Accelerated life test of MRAM cells

2005-05-17

2005-05-17

Elms, Richard (Department: 2824)

Static information storage and retrieval

Read/write circuit

Testing

C365S189090, C365S185230, C327S530000

Reexamination Certificate

active

06894937

ABSTRACT:
A circuit provides a stress voltage to magnetic tunnel junctions (MTJs), which comprise the storage elements of a magnetoresitive random access memory (MRAM), during an accelerated life test of the MRAM. The stress voltage is selected to provide a predetermined acceleration of aging compared to normal operation. A source follower circuit is used to apply a stress voltage to a subset of the memory cells at given point in time during the life test. The stress voltage is maintained at the desired voltage by a circuit that mocks the loading characteristics of the portion of the memory array being stressed. The result is a closely defined voltage applied to the MTJs so that the magnitude of the acceleration is well defined for all of the memory cells.

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patent: 20030058717 (2003-03-01), Kawamoto

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