Accelerated hierarchical address filtering and translation using

Details Accelerated hierarchical address filtering and translation using Accelerated hierarchical address filtering and translation using

1997-03-14

1999-07-06

Chan, Eddie P.

Electrical computers and digital processing systems: memory

Storage accessing and control

Specific memory composition

711206, 365168, G06F 1210

Patent

active

059208864

ABSTRACT:
A method and apparatus are provided for performing hierarchical address translation by translating each ternary hierarchical address into a binary address and a binary priority mask and storing the binary addresses in the binary CAM. A binary search of the priority masks is then performed by searching the CAM with a priority mask and choosing a next priority mask depending on the results of the search of the CAM until a correct matching entry (i.e., the matching entry with the lowest hierarchical level) is found. This technique only requires log.sub.2 N searches of the CAM, where N is the number of hierarchical levels represented by the priority field. A method and apparatus are also provided for performing hierarchical address translation by storing table entries including a priority field in a ternary CAM and performing only a fixed number of searches of the CAM. Finally, a method and apparatus are provided for storing a translated hierarchical address in a cache CAM and using the cache CAM to perform successive hierarchical address translations.

REFERENCES:
patent: 5329618 (1994-07-01), Moati et al.
patent: 5386413 (1995-01-01), McAuley et al.
patent: 5414704 (1995-05-01), Spinney
patent: 5422838 (1995-06-01), Lin
patent: 5568415 (1996-10-01), McLellan et al.

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