Accelerated graphics port expedite cycle throttling control...

Details Accelerated graphics port expedite cycle throttling control... Accelerated graphics port expedite cycle throttling control...

1998-03-02

2004-08-31

Chauhan, Ulka J. (Department: 2676)

Computer graphics processing and selective visual display system

Computer graphics display memory system

Graphic display memory controller

C345S503000, C345S520000, C345S531000, C711S150000, C711S151000, C710S241000

Reexamination Certificate

active

06784890

ABSTRACT:

BACKGROUND OF THE INVENTION
(1) Field of the Invention
The field of the invention is data access control in computer systems; more specifically, the present invention is related to a method and apparatus for an accelerated graphics port (AGP) expedite cycle throttling control mechanism.
(2) Related Art
Currently available computer systems typically have a graphics device capable of processing graphics data for display on a display device. In order to provide an uninterrupted flow of graphics data for display on a display device, a graphics device must be given high priority to access the system memory for graphics instructions and data. Other devices also vying for the system memory may then be potentially starved out during long streams of graphics cycles to the system memory by the graphics device.
To overcome this problem, the prior art stops the graphics cycles from further processing if the graphics cycles continue consecutively for more than a predetermined period. The disadvantage of the prior art is that there can be as few as one clock cycle with no graphics cycles during the predetermined period and the remaining time in the predetermined period may be devoted to graphics cycles preventing other devices from accessing the system memory.
It is therefore desirable to have a method and apparatus which guarantees a specified period of time for non graphics cycles to be processed. This protects latency sensitive devices from undue delay in accessing a system memory while minimizing added latency to graphics cycles.
BRIEF SUMMARY OF THE INVENTION
A method for controlling expedite cycles having the steps of determining the number of clock cycles devoted to expedite data transfer requests made to a component during a predetermined monitoring window and guaranteeing a minimum number of clock cycles for processing non-expedite requests during the monitoring window.


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