Electrical computers and digital data processing systems: input/ – Intrasystem connection – Bus interface architecture
Reexamination Certificate
2001-02-07
2004-01-06
Auve, Glenn A. (Department: 2182)
Electrical computers and digital data processing systems: input/
Intrasystem connection
Bus interface architecture
Reexamination Certificate
active
06675252
ABSTRACT:
FIELD OF THE INVENTION
The invention is generally related to electronic bus architectures and like interconnects, and in particular, to supporting fast write transactions with an Accelerated Graphics Port (AGP) controller.
BACKGROUND OF THE INVENTION
As computers and other electronic devices are called upon to handle increasingly difficult tasks, greater and greater performance demands are placed on such devices. Of particular concern in many devices, for example, is the communications speed, or “bandwidth”, between interconnected devices, as the speed in which information is transmitted between such devices can have a significant impact on the overall performance of an electronic system.
A number of different interconnection standards have been developed over the years to support the ever-increasing communication needs of computers and other electronic devices. For example, the Peripheral Component Interconnect (PCI) standard was developed to interconnect external devices with the central processing unit (CPU) of a computer. PCI interconnects, or buses, interface with a CPU via a bridge to the local bus for the CPU, and PCI-compatible devices such as audio processors, storage controllers, graphics controllers, network adaptors, etc. are coupled to the bus.
While the PCI standard represented a significant improvement over prior technologies, and despite the fact that the PCI standard has been revised to support greater bandwidth capacity, the increasing input/output requirements of modern computers have necessitated the development of additional interconnect technologies.
For example, the Accelerated Graphics Port (AGP) standard has been developed as an extension of the PCI standard to provide a dedicated high speed interconnect for transmitting graphical data between a graphics accelerator or controller (functioning as an AGP-compatible device) and a system memory, without the need for CPU intervention. Many graphical applications, in particular 3D applications, have relatively high memory bandwidth requirements, and an AGP-compatible interconnect, or bus, assists in accelerating the transfer of graphical data in such memory-intensive applications.
To support the PCI and AGP standards, a computer generally relies on the use of a chipset, also known as corelogic, to provide the interface between the CPU, system memory, AGP bus and PCI bus. For interconnection with an AGP bus, the corelogic includes an AGP controller that is required to handle both AGP-type and PCI-type transactions. An AGP master (e.g., a graphics controller) can transfer data to a system memory using either AGP or PCI transactions, while a CPU can access an AGP master using only PCI transactions, whereby the AGP master can also operate as a PCI target.
Given that an AGP bus is a dedicated, direct connection, the CPU is typically not involved in data transfers between an AGP-compatible device and system memory. As a result, in many instances PCI operations, as well as CPU accesses to the memory, can occur in parallel with AGP operations.
Many graphics operations, however, still require CPU involvement, and as such, the initial interface specification for the AGP standard, Revision 1.0, permits a CPU to write data to an AGP-compatible device through a two step procedure. Essentially, a CPU is required to write data into the system memory, and then direct (via a PCI transaction) that an AGP-compatible device read the data from the system memory.
Beginning with Revision 2.0, however, the AGP Specification has supported the concept of a fast write transaction. With a fast write transaction, data is transferred directly from the CPU to an AGP-compatible device, instead of requiring the data to be written into, and subsequently read out of, system memory. Revision 2.0 of the AGP Specification supports fast write transactions at 2× and 4×speeds (i.e., two or four times the clock frequency of the AGP bus).
Normal PCI write transactions occur at 1×speed, and follow PCI coherency and ordering rules. For AGP fast write transactions, however, a combination of PCI and AGP bus protocols is used, whereby a PCI-type transaction is used to initiate the transaction, and data flow generally occurs based on an AGP-type protocol. Thus, the interface to an AGP bus (often referred to as an AGP controller) for a corelogic design typically must include both PCI and AGP transaction-handling circuitry.
Implementing AGP fast write support in an AGP controller of a corelogic design, however, can be problematic, particularly when attempting to revise a prior corelogic design. In particular, as integrated circuits have become more and more complex, the development time and costs associated with designing and testing integrated circuit designs have also increased. Whenever possible, a modular “building block” approach is used, whereby a design is constructed from previously developed and tested circuit blocks. When a design is assembled from pre-existing blocks, often the amount of custom circuitry that needs to be created is reduced, as is the amount of testing that is required to verify that a design will function properly.
Support for full AGP 2.0 fast write functionality in an AGP-compatible corelogic design (e.g., to support 2× or 4×, or “multiplied” AGP fast write transactions), however, has conventionally required a substantial amount of custom design, as prior corelogic circuit blocks have not been found to be particularly reusable. As one example, a circuit block that functions as a PCI target or master would typically require the addition of circuitry to handle 2× and 4×data flow in order to be useful in an AGP 2.0 controller implementation. Adding such functionality would be time consuming and costly, and moreover, would reduce the portability of the design for use in other applications, e.g., as a standard PCI block. Moreover, since AGP logic requires high frequency 2×/4×outer timing loop circuitry, implementing fast write functionality within a PCI circuit block would add additional data paths to the extremely timing critical high frequency data path.
As another example, the AGP 2.0 Specification supports the concept of multi-block transfers via multiplied fast write transactions. A block in this context is the amount of data capable of being transferred in four clock cycles (typically 32 bytes at 2×speed and 64 bytes at 4×speed). In a multi-block multiplied AGP fast write transfer, throttling is performed on a per block basis, which is similar to other AGP transactions, but is substantially different from PCI transactions. Implementing the support for multi-block transfers in a fully compatible AGP 2.0 corelogic design therefore requires that the PCI-handling circuitry in an AGP controller be capable of throttling a multi-block transaction. Moreover, whenever multi-block transfers are permitted, various exceptional circumstances must be handled, e.g., abort conditions, disconnect conditions, etc. This additional functionality increases the complexity of the AGP controller circuitry, and thus increases development time and costs, and reduces design portability, due to the inability to reuse prior designs.
Therefore, a significant need exists in the art for an AGP controller design that supports fast write functionality with substantially less complexity and effort than has heretofore been required.
SUMMARY OF THE INVENTION
The invention addresses these and other problems associated with the prior art by providing in one aspect a circuit arrangement and method in which the data path used during the processing of multiplied (e.g., 2× or 4×) AGP fast write transactions is implemented within a circuit block outside of the PCI circuit block conventionally used to handle the address phases of such transactions. Rather than implementing the data path within the PCI circuit block, a control path is defined between the PCI circuit block and the other circuit block to permit the PCI circuit block to initiate the data phase of the multiplied AGP fast write trans
Auve Glenn A.
Zawilski Peter
LandOfFree
Accelerated graphics port (AGP) controller supporting fast... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Accelerated graphics port (AGP) controller supporting fast..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Accelerated graphics port (AGP) controller supporting fast... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3264554