Static information storage and retrieval – Systems using particular element – Ferroelectric
Reexamination Certificate
2002-07-02
2004-05-11
Auduong, Gene (Department: 2818)
Static information storage and retrieval
Systems using particular element
Ferroelectric
C365S149000, C365S189040, C365S201000
Reexamination Certificate
active
06735106
ABSTRACT:
BACKGROUND
Integrated circuit manufacturers often test integrated circuits and attempt to identify chips having latent defects that may lead to unacceptably short useful lifetimes. One example of an integrated circuit requiring such testing is a ferroelectric random access memory (FeRAM). A FeRAM generally includes an array of memory cells where each memory cell contains at least one ferroelectric capacitor. Each ferroelectric capacitor contains a ferroelectric material sandwiched between conductive plates. To store a data bit in a FeRAM cell, a write operation applies write voltages to the plates of the ferroelectric capacitor in the FeRAM cell to polarize the ferroelectric material in a direction associated with the data bit being written. A persistent polarization remains in the ferroelectric material after the write voltages are removed and thus provides non-volatile storage of the stored data bit.
A conventional read operation for a FeRAM determines the data bit stored in a FeRAM cell by connecting one plate of a ferroelectric capacitor to a bit line and raising the other plate to a read voltage. If the persistent polarization in the ferroelectric capacitor is in a direction corresponding to the read voltage, the read voltage causes a relatively small current through the ferroelectric capacitor, resulting in a small charge and voltage change on the bit line. If the persistent polarization initially opposes the read voltage, the read voltage flips the direction of the persistent polarization, discharging the plates and resulting in a relatively large charge and voltage increase on the bit line. A sense amplifier can determine the stored value from the resulting bit line current or voltage.
Repeated reading and writing of a FeRAM cell, which changes the polarization state of the ferroelectric capacitor, can fatigue the ferroelectric material and change the properties of the FeRAM cell. The resulting fatigue may eventually lead to a failure. One way to predict when a particular FeRAM cell may fail is to measure the properties on the FeRAM cell before and after performing a series of read and write operations on the FeRAM cell. A measured change in the properties of the FeRAM cell can then be extrapolated to the desired minimum life of the FeRAM cell to project whether the FeRAM cell will still be operable. If the extrapolation indicates that the FeRAM cell will fail before reaching the desired minimum life, the FeRAM cell may have a latent defect and may be replaced with redundant FeRAM cells in a memory device.
The minimum number of read or write cycles before a failure of a FeRAM cell must be large (e.g., on the order of 10
15
cycles or more) to provide a memory device with a commercially viable life. The large number of cycles before failure can make fatigue testing very time consuming. Extrapolation to 10
15
read/write cycles, for example, might reasonably require a test to actually perform 10
12
read/write cycles on a FeRAM cell. However, performing 10
12
read and write operations on every memory cell in a reasonable size FeRAM (e.g., in a 4-megabit FeRAM) would literally require days, making such testing impractical for production testing of FeRAM and at least bothersome when testing a FeRAM design. Extrapolation can be based on a smaller number of read and write cycles per FeRAM cell to reduce the testing time, but reduction of the number of cycles reduces the accuracy of the test.
U.S. Pat. No. 6,314,018 describes a FeRAM having a test mode of operation that can speed up fatigue testing. This FeRAM uses a specific FeRAM architecture capable of pulsing two plate segments simultaneously in the test mode and a single plate segment in a normal mode. The test mode thus simultaneously accesses a larger number of FeRAM cells than can read or write operations in the normal mode.
In view of the need for accurate testing in order to provide reliable FeRAM, improved architectures and processes that permit fatigue testing within commercially expedient times are sought.
SUMMARY
In accordance with an aspect of the invention, a FeRAM has an architecture implementing a set of test modes that accelerate fatigue testing. One test mode uses decoding for standard read/write operations in each section of the FeRAM but simultaneously exercises all sections. Another test mode simultaneously exercises one row per plate-line group for all plate-line groups and all segments. The same row can be repeatedly exercised to heavily fatigue (e.g., 10
14
cycles) a portion of the FeRAM, or the rows of the plate line groups can be sequentially exercised to fatigue test a larger number of FeRAM cells.
One specific embodiment of the invention is an integrated memory such as a FeRAM. The memory includes: multiple segments, where each segment contains bit lines and memory cells connected to the bit lines. An address decoding circuit for the memory has a first mode for read and write operations, and in the first mode, the address decoding circuit selects one of the segments and makes the memory cells in the selected segment accessible. The address decoding circuit has a second mode for accelerated fatigue operations, and in the second mode, the address decoding circuit selects all of the segments so that memory cells in all of the segments are simultaneously accessible for a change in state. In the first mode, the address decoding circuit generally makes only the bit lines in the selected segment accessible, but in the second mode, the address decoding circuit activates drive circuits for all of the bit lines.
For a FeRAM, each memory cell generally includes a select transistor and a ferrorelectric storage capacitor, and each of the segments includes plate lines that are connected to respective subsets of the memory cells. The select transistor in a memory cell connects one plate of the storage capacitor to a corresponding bit line, and each plate line connects to the other plate of each storage capacitor in the memory cells corresponding to the plate line. In the second mode, the address decoding circuit either activates only one of the plate lines in each segment or alternatively activates all of the plate lines. Activating all of the plate lines allows simultaneously changing the states of more FeRAM cells, but generally requires more bit line current to flip the polarization state of multiple FeRAM cells coupled to each bit line.
Another embodiment of the invention is a FeRAM including one or more memory sections, a first address decoding circuit, and a second address decoding circuit. Each memory section includes memory cells, bit lines, and word lines. The memory cells are arranged in rows and columns with each row of memory cells being connected to a corresponding one of the word lines and each column of memory cells being connected to a corresponding one of the bit lines. Each memory section is further divided into segments with each segment including the bit lines and the memory cells in a set of the columns. Each segment further includes plate lines and drive circuits with the drive circuits being respectively connected to the plate lines in the segment. The first address decoding circuit generates segment select signals, and the second address decoding circuit generates plate line select signals. Each plate line drive circuit drives the connected plate line in response to activation of both the segment select signal corresponding to the segment containing the drive circuit and the corresponding plate line select signal.
Test modes of the first and second decoding circuits implement accelerated fatigue operations. In particular, the first address decoding circuit can have a normal mode in which the first address decoding circuit activates only one of the segment select signals and a test mode in which the first address decoding circuit simultaneously activates all of the segment select signals. Similarly, the second address decoding circuit can have a normal mode in which the second address decoding circuit activates only one of the plate line select signals and a test mode in which the seco
Fong John Y.
Grace James W.
Lanham Ralph H.
McAdams Hugh P.
Rickes Juergen T.
Agilent Technologie,s Inc.
Auduong Gene
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