AC parametric circuit having adjustable delay lock loop

Details AC parametric circuit having adjustable delay lock loop AC parametric circuit having adjustable delay lock loop

1983-08-26

1985-07-02

Miller, Stanley D.

Electrical transmission or interconnection systems

Nonlinear reactor systems

Parametrons

307511, 307516, 307263, 307603, 324 73R, 328 55, 328 74, 328133, 328185, H03K 5153

Patent

active

045271267

ABSTRACT:
An improved delay lock loop which has first and second means (32, 34) for generating a voltage ramp, the first ramp generator (32) providing a train of ramped inputs to first time delay means (38) responsive to a first input pulse train and the second ramp generator (34) providing a train of ramped inputs to a second time delay means (40) responsive to a second input pulse train. The ramp generators (32, 34) provide a highly linear voltage ramp. First and second retrace means (36A, 36B) are connected to the first and second ramp generators (32, 34) respectively and act to limit the ramps to a certain voltage, commanding the ramp generators (32, 34) to return to a reference voltage to await the succeeding input pulse edge transition. A further improvement comprises range switch means (44) that function to selectively control the maximum range of time delay which the delay lock loop is able to sense. This permits selecting a greater or lesser range of time which the delay in time intervals between the edge transitions of the pulses in the first and second input pulse in the first and second input pulse trains can have and still be measured. Additionally, calibrator means (26) are incorporated which provide signals to the delay lock loop and ancillary electronics to determine the delay inherent in these devices. This delay is stored and subtracted from the delay determined by the delay lock loop to increase the accuracy. The calibrator (26) additionally very accurately determines the voltage difference between the voltage representing zero volts on the ramp and the voltage representing full scale on the ramp to very accurately determine the voltage span representative of the selected range.

REFERENCES:
patent: 3790767 (1974-02-01), Alexander
patent: 4092589 (1978-05-01), Chau et al.
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patent: 4309673 (1982-01-01), Norberg et al.
patent: 4338569 (1982-07-01), Petrich
patent: 4392105 (1983-07-01), McLeod
patent: 4403193 (1983-09-01), Takemura
patent: 4449059 (1984-05-01), Dickes
patent: 4481647 (1984-11-01), Gombert et al.
patent: 4488297 (1984-12-01), Vaid
Burdett et al, "All Net Probe Card Testing", IBM Tech. Disc. Bull., vol. 20, No. 6, Nov. 1977, pp. 2358-2359.
Geffken, "Variable Parameter Tester Control System", IBM Tech. Disc. Bull., vol. 20, No. 7, Dec. 1977, pp. 2596-2598.

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