Electronic digital logic circuitry – Clocking or synchronizing of logic stages or gates
Reexamination Certificate
2001-03-27
2003-02-11
Le, Don (Department: 2819)
Electronic digital logic circuitry
Clocking or synchronizing of logic stages or gates
C326S083000
Reexamination Certificate
active
06518794
ABSTRACT:
FIELD OF THE INVENTION
The invention relates to the method and apparatus used for communication between two or more semiconductor devices. In particular it relates to the calibration of output circuits for CMOS devices, to improve the uniformity of timing of signaling which is adversely effected by changes in temperature, voltage, processing conditions, properties of the conducting media between driving and receiving circuits, and properties of the receiving circuits.
BACKGROUND
As progress in the art evolves uniformity of CMOS driven circuitry performance is taking on increased importance.
In one reference, an IBM brochure labelled 8 Mb(256K×36 & 512×18) and 4 Mb 128K×36&256K×18)SRAM, trrn 3316.04, 7/99,25 pages; there is described a method for the DC adjustment of output impedance. The adjustment allows the impedance on the pullup and pulldown devices in a standard CMOS output driver circuit to be made equal to each other, and to a fixed external reference
In another reference, a SLDRAM Inc. brochure, labelled 400 Mb/s/pin 4 M×18 SLDRAM, Rev Jul. 9, 1998, 69 pages: another method of calibration allows output devices to present equal switching levels to a receiver for both high to low (H—>L) and low to high (L—>H) transitions. However, in these methods the time with which these switching levels are reached is not specified or calibrated.
Recently in the art, new signaling between CMOS devices has been introduced where a sending chip sends both data and a strobe waveform with data to be received by one or more receiving chips, whereby the strobe can capture data either on both 1—> and h—>1 transitions. Such a memory device is described in a an IBM brochure labelled 256 Mb Double Data Rate Synchronous DRAM, 29L0011.E36997, Apr. 3, 2000, 81 pages. With the Double data rate type comments described, any difference in time of arrival of l—>h and h—>1 transitions at the receiver can seriously limit the signaling rate. The transmission rate of the device in the Double Data Rate reference is limited to a 266 MHz rate, where each data bit is sent as a 1 or 0 on a single wire, in coincident with a strobe signal, alternating 1 and 0, on another wire. The value of the datum sent on the wire, 1 or 0, is determined by comparing the sampled voltage to a reference voltage at the receiver.
In the art there is a desire to transmit data at faster rates, however, lack of adequate controls on the time of arrival of data with respect to the strobe, and with respect to the reference voltage, can limit progress. What is needed is a simple means to adjust and control the time of arrival of data or strobe for both the 1 and 0 state, so that transmission speeds can be increased.
SUMMARY
The invention teaches a technique for A C equilibration of the signaling levels and time of 1—>h and h—>1 transitions of CMOS drivers as received at CMOS receivers, so as to improve the rate at which data can be communicated between two CMOS devices.
REFERENCES:
patent: 5309035 (1994-05-01), Watson et al.
patent: 5602512 (1997-02-01), Neron
patent: 6100733 (2000-08-01), Dortu et al.
IBM 8Mb(256K×36&512×18)And 4Mb (128K×36&256K×18) SRAM Brochure, trrn 3316.04, 7/99, 25 pages.
SLDRAM Inc. Brochure, 400Mb/S/pin 4M×18SLDRAM, Rev Jul. 9, 1998, 69 pages.
IBM 256 Mb Double Data Rate Synchronous DRAM Brochure, 29L0011.E36997, Apr. 3, 2000, 81 pages.
Coteus Paul William
Gara Alan Gene
Le Don
Morris Daniel P.
Riddles Alvin J.
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