Error detection/correction and fault detection/recovery – Pulse or data error handling – Memory testing
Reexamination Certificate
2011-04-19
2011-04-19
Trimmings, John P (Department: 2117)
Error detection/correction and fault detection/recovery
Pulse or data error handling
Memory testing
C714S721000, C714S719000, C714S720000, C714S718000, C714S726000, C714S005110, C714S006130, C714S025000, C714S030000, C714S042000, C714S048000, C714S733000, C714S734000, C714S735000, C714S736000, C714S742000, C365S201000
Reexamination Certificate
active
07930601
ABSTRACT:
A method for implementing at speed bit fail mapping of an embedded memory system having ABIST (Array Built In Self Testing), comprises using a high speed multiplied clock which is a multiple of an external clock of an external tester to sequence ABIST bit fail testing of the embedded memory system. Collect store fail data during ABIST testing of the embedded memory system. Perform a predetermined number of ABIST runs before issuing a bypass order substituting the external clock for the high speed multiplied clock. Use the external clock of the tester to read bit fail data out to the external tester.
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Eckelman Joseph
Forlenza Donato O.
Forlenza Orazio P.
Hurley William J.
Knips Thomas J.
International Business Machines - Corporation
Kinnaman, Jr. William A.
Trimmings John P
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