Electrical computers and digital data processing systems: input/ – Input/output data processing – Input/output process timing
Reexamination Certificate
1999-11-17
2004-05-04
Lefkowitz, Sumati (Department: 2181)
Electrical computers and digital data processing systems: input/
Input/output data processing
Input/output process timing
C710S052000, C710S029000, C710S074000, C710S305000
Reexamination Certificate
active
06732200
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a data processing circuit and a data transmission system.
2. Description of the Related Art
As an interface for multimedia data transfer, an IEEE (The Institute of Electrical and Electronic Engineers) 1394 serial interface which realizes high speed data transfer and real-time transfer has recently been standardized.
The data processing circuit of such an IEEE 1394 serial interface is mainly comprised of a physical layer circuit for directly driving an IEEE 1394 serial bus and a link layer circuit for controlling the data transfer of the physical layer. The physical layer circuits of a plurality of data processing circuits are connected through the IEEE 1394 serial bus and one or more applications are connected to the link layer circuits of the data processing circuits.
As applications, a CD (compact disk) player or MD (Mini Disc) player or other multimedia equipment, speakers, various computers, set top boxes, and other consumer products and hard disk drives and other data storage apparatuses etc. may be exampled.
In a system using the above IEEE 1394 serial interface, normally, asynchronous transfer for requesting data and confirming receipt and isochronous transfer for transferring data forcibly once every 125 &mgr;s are performed between an application connected to one data processing circuit and another application connected to another data processing circuit through the IEEE 1394 serial bus, and it is also possible to transfer data between a plurality of applications connected to one data processing circuit.
For example, it is possible to connect a CD player and a speaker to one data processing circuit to output digital audio data input from the CD player to the speakers and to convert a data of an analog format at a digital-to-analog (D/A) converter at the speakers and to thereby output sound according to the analog audio data.
When the frequency of the clock signal used at the D/A converter of the speaker is higher than the frequency of the clock signal used at the time of reproduction of the digital audio data at the CD player, a sampling rate converter (SRC) was used to compensate the audio data output from the CD player and output the compensated audio data to the speaker.
Summarizing the problems to be solved by the invention, as explained above, however, since an SRC was used, there was the problem that the system became larger in size and higher in price.
Further, it is possible to connect various applications operating at mutually different frequencies to the data processing circuit of an IEEE 1394 serial interface. It is not easy to determine the sampling rate of the SRC built in the data processing circuit.
Further, when transmitting data from one data processing circuit to another data processing circuit through the IEEE 1394 serial interface, a similar problem as explained above exists also when the operating frequencies of the application connected to the one data processing circuit and the application connected to another data processing circuit differ.
SUMMARY OF THE INVENTION
An object of the present invention is to provide a data processing circuit able to absorb the jitter due to the difference in operating frequencies between applications by a small sized and inexpensive configuration when connecting a plurality of applications operating at diverse frequencies.
Another object of the present invention is to provide a data processing circuit and data transmission system able to absorb jitter due to differences in operating frequencies of applications between a transmitting side and receiving side when transmitting data through a data transmission channel.
To solve the above problems and achieve the above objects, a data processing circuit according to a first aspect of the present invention is a data processing circuit for connecting a plurality of applications including a first application and a second application operating on the basis of clock signals of different frequencies, comprising a storage circuit and a storage control circuit for storing data input from the first application in the storage circuit on the basis of a first clock signal set for the operating frequency of the first application and then reading it out on the basis of a second clock signal set for the operating frequency of the second application.
In the data processing circuit of the first aspect of the present invention, data is input from the first application operating on the basis of the first clock signal and the input data is written by the storage control circuit in the storage circuit on the basis of the first clock signal.
Next, the data is read by the storage control circuit from the storage circuit on the basis of the second clock signal and the read data is output to the second application. At this time, the read operation of the data from the storage circuit is performed on the basis of the second clock signal serving as the basis of the operation of the second application, so the read data is processed at a high accuracy in the second application.
Further, by using a storage circuit absorbing the deviation between the first clock signal and the second clock signal (jitter) in this way, the size can be reduced and the cost lowered compared with the case of use of a conventional sampling rate converter.
Further, the data processing circuit of the first aspect of the present invention preferably further comprises an application control circuit for monitoring the storage state of the storage circuit and controlling the amount of the data which the first application outputs per unit time on the basis of the results of the monitoring. Further, the application control circuit controls the amount of the data which the first application outputs so that the storage circuit does not overflow or underflow.
Due to this, it is possible to avoid the storage circuit overflowing or underflowing and possible to ensure the continuity of the processing in the second application.
Further, a data processing circuit according to a second aspect of the present invention is a data processing circuit for outputting data received from another data processing circuit connecting a first application through a data transmission channel to a second application, comprising a receiving circuit for receiving data from the data transmission channel and reproducing a first clock set for an operating frequency of the first application carried in the received data, a storage circuit, and a storage control circuit for writing the received data in the storage circuit on the basis of the reproduced first clock signal and then reading it out on the basis of a second clock signal set for the operating frequency of the second application and outputting it to the second application.
In the data processing circuit of the second aspect of the present invention, data is received by the receiving circuit from the data transmission channel and the first clock signal carried in the received data is reproduced.
Next, the received data is written by the storage control circuit in the storage circuit on the basis of the reproduced first clock signal, then is read out on the basis of the second clock signal of a frequency different from the first clock signal and output to the second application.
Further, a data processing circuit according to a third aspect of the present invention is a data processing circuit for outputting data input from a first application through a data transmission channel to a second application connected to another data processing circuit, comprising a storage circuit, a storage control circuit for storing the data input from the first application to the storage circuit on the basis of a first clock signal set for the operating frequency of the first application and then reading it out on the basis of a second clock signal set for the operating frequency of the second application, and a transmission circuit for transmitting the data read out from the storage circuit through the data transmission channel to the
Frommer William S.
Frommer & Lawrence & Haug LLP
Lefkowitz Sumati
Polito Bruno
Sony Corporation
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