Electrical computers and digital processing systems: memory – Address formation – Address mapping
Reexamination Certificate
2002-01-09
2004-06-01
Moazzami, Nasser (Department: 2187)
Electrical computers and digital processing systems: memory
Address formation
Address mapping
C712S233000, C712S240000
Reexamination Certificate
active
06745313
ABSTRACT:
BACKGROUND
There are a variety of ways to organize and access data in cache memories. In some processors, the cache data is organized by absolute address rather than by virtual address. The absolute address is the address at which the data is located in main storage, and the virtual address is the address at which the data is located relative to the calling program. However, when data is to be fetched from the cache, the only address initially available is the virtual address. Because of the size of the cache and because some bits of the address may be changed during translation from the virtual address to the absolute address, some bits of the translated absolute address that are needed to uniquely define the location of the desired data in the cache are not available in the virtual address. The correct absolute address bits are held in the translation look-aside buffer (or “TLB”). Since accessing the translation look-aside buffer is done at the same time as the reading of the cache directory and data, the absolute address bits needed from the translation look-aside buffer to find the data in the cache are not available in time for the initial cache access.
This problem has existed on some processors for many years. The problem has been handled by reading from every location in the cache that the desired data could have been, and then sorting out the particular piece of desired data after all of the address information became available. This took a lot of comparison circuits and had a potential impact on the cycle time of the processor. The IBM® Alliance® processors introduced a structure called an absolute address history table (or “AAHT”) to predict the values of the absolute address bits that were needed. Unfortunately, the prior solutions did not adequately predict absolute address bits for accessing an instruction cache in the case of branch instructions.
SUMMARY
This disclosure presents a method for selecting data in a computer system having a cache memory and a branch history table where the method includes predicting an address corresponding to the data, selecting data at the predicted address in the cache memory, translating an address corresponding to the data, comparing the translated address with the predicted address, and if they are different; re-selecting data at the translated address in the cache memory and appending the translated address to the branch history table.
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Check Mark A.
Liptay John S.
Liptay Lynne M.
Prasky Brian R.
Shum Chung-Lung Kevin
Augspurger Lynn
Liptay Lynne M.
Moazzami Nasser
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