Measuring and testing – Inspecting
Reexamination Certificate
2002-05-24
2004-03-23
Niebling, John F. (Department: 2812)
Measuring and testing
Inspecting
C250S491100
Reexamination Certificate
active
06708574
ABSTRACT:
FIELD OF THE INVENTION
This invention relates in general to the field of semiconductor manufacturing. More particularly, this invention relates to method for analyzing a semiconductor surface with patterned features using line width metrology.
BACKGROUND OF THE INVENTION
Semiconductor manufacturing consists of a number of crucial processing steps performed on wafer lots. Fabrication processes use tools that communicate in a manufacturing framework or network. This network along with manufacturing model script software establishes a process control system. As semiconductive materials are staged through processes in this system, data relating to quality is collected. Frequent processing errors are typical in this system, which causes appreciable inconsistencies in critical dimensions of semiconductive material.
Once the wafers have patterned features, analysis of semiconductor surface quality can be performed using line width metrology. Manufacturing issues often result in inferior quality of a feature's sidewalls. Additionally, it is desirable that there be a minimal amount of scumming and residual at the bottom of a feature. As the number of features on a substrate and the complexity of the features increase, methods must be developed to ensure that user specified critical dimensions can be consistently and accurately achieved. The need for error reduction also increases substantially as technology facilitates smaller critical dimensions for semiconductive devices.
One approach has been to utilize software to compare critical dimensions of waveform profiles to a known master database of deviant profiles. In this approach, critical dimensions for all possible defects must be captured and archived in the database through an exhaustive range of both shapes and scales. Each waveform is unique to the technology and metrology tool used. The database must be vigorously maintained for each geometry and substrate as well. The software can identify any correlation of a whole signal profile to one found in the database. Detection requires whole signal correlation and does not accommodate for variations in scale as well as unarchived shapes. This solution results in a high degree of false detections. Due to inadequate performance, this method has not been implemented in a fabrication facility.
Other traditional in-line metrology measures a photoresist line width regardless of the semiconductor profile. However, a profile strongly influences the pattern transfer and needs to be accounted for in small device geometries. This invention enables the recognition of abnormal profiles, ranks the deviation magnitude, and enables the in-line metrology system to correct the root cause before committing lots to etch.
SUMMARY OF THE INVENTION
An object of the present invention is to streamline semiconductor-manufacturing processes, increase product yield rates, solve the need for greater precision, and induce process reliability/repeatability by automating processes thus reducing the need for human involvement.
Another object of the present invention is to provide a method for automatically determining acceptability of a semiconductor surface having a patterned feature using line width metrology signal processing.
Another object of this invention is to recognize and respond to the scumming defect where spaces are not adequately cleared between lines.
Another object of the present invention is to provide universal applicability to a wide range of technologies, metrology tools, and process control systems via the application of the method disclosed of applying a curve-fit function to known signal characteristics which is independent of process variations of both shape and scale.
Yet another object of the present invention is to provide a solution that does not need to “learn” what a normal waveform profile is as it depends on scale independent numerical relations to detect specific features by using known geometric shapes to determine the presence of specific features.
In accordance with the present invention, the disclosed method enables process automation for semiconductor fabrication by employing geometric shapes also known as curve-fit functions to analyze a semiconductor surface quality using line width metrology. This is accomplished by analyzing a patterned feature formed on a semiconductor layer. At least one patterned feature is scanned to generate an amplitude modulated waveform signal of the line and neighboring space characteristics. Signal processing is automatically performed on this waveform by an in-line computational source to extract known patterned features based on a profile of the amplitude modulated waveform signal. Software performs the classification thus automating the process. The extracted waveform segments are subjected to curve-fit functions to determine if the waveform indicates a normal or abnormal patterned feature on a semiconductor layer which relates directly to acceptability of the patterned feature quality. Once the waveform has been classified a lot of wafers being processed can be dispositioned for further processing or rework (i.e., acceptable or not acceptable).
REFERENCES:
patent: 4983253 (1991-01-01), Wolfe
patent: 5969273 (1999-10-01), Archie
patent: 6407396 (2002-06-01), Mih
Houge Erik Cho
Jessen Scott
McIntosh John Martin
Stevie Fred Anthony
Vartuli Catherine
Agere Systems Inc.
Beusse James H.
Beusse Brownlee Bowdoin & Wolter P.A.
Niebling John F.
Stevenson André C
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