Error detection/correction and fault detection/recovery – Pulse or data error handling – Memory testing
Reexamination Certificate
2006-07-04
2006-07-04
Decady, Albert (Department: 2138)
Error detection/correction and fault detection/recovery
Pulse or data error handling
Memory testing
C711S217000
Reexamination Certificate
active
07073105
ABSTRACT:
An array built-in, on-chip self test system for testing a memory array and a method of testing the memory array. The memory array has data input ports, data output ports, and address ports, and a data control subsystem, an address control subsystem, and a comparator. The data control subsystem generates and applies deterministic data patterns to the data input ports of the memory array. The address control subsystem generates addresses for application to the memory array in coordination with said data control subsystem, and includes a sequence counter, a count rate controller for the sequence controller, a count rate controller divider to control the number of cycles per address, an address controller to provide granular control of addresses, and an X-OR gate receiving an input from a sequence counter and from the address controller, the X-OR gate outputting an address bit to the memory array. The comparator compares the data inputted to the data input ports of the memory array from the data control subsystem with the data outputted from the data output ports of the memory array.
REFERENCES:
patent: 6079006 (2000-06-01), Pickett
patent: 6631086 (2003-10-01), Bill et al.
patent: 6829181 (2004-12-01), Seitoh
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patent: 2004/0205435 (2004-10-01), Knips et al.
“Optimization of Address Generator Hardware” by Grant et al.European Design and Test Conference, The European Conference on Design Automation. ETC European Test Conference. Proceedings.Publication Date: Feb. 28-Mar. 3, 1994 p. 325-329.
Davis John D.
Dawson James W.
Knips Thomas J.
Malone Douglas J.
Augspurger Lynn L.
Britt Cynthia
De'cady Albert
Goldman Richard M.
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