Fishing – trapping – and vermin destroying
Patent
1987-02-17
1988-05-24
Chaudhuri, Olik
Fishing, trapping, and vermin destroying
437 67, 437233, 437238, 156653, H01L 21425, H01L 21473
Patent
active
047466251
ABSTRACT:
A semiconductor manufacturing method which comprises the steps of forming a polycrystalline silicon layer on a semiconductor substrate; depositing a silicon oxide layer on the polycrystalline silicon layer; mounting an acidproof layer on the silicon oxide layer; selectively eliminating the acidproof layer deposited on a semiconductor element-isolating region by the photoetching process; selectively eliminating the silicon oxide layer with the retained acidproof layer used as a mask; ion implanting a channel stopper impurity in the semiconductor substrate through the masks formed of a photoresist coated on the acidproof layer the acidproof layer, and silicon oxide layer; eliminating the photoresist; selectively depositing a silicon layer on the exposed polycrystalline silicon; carrying out thermal oxidation with the acidproof layer used as a mask; eliminating the acidproof layer; filling an oxide in the cavities of the side walls of the semiconductor element-isolating insulation layer; and exposing by etching that portion of the semiconductor substrate which will constitute a semiconductor element region, thereby forming a thick semiconductor element-isolating layer with high precision in a narrow semiconductor element-isolating region.
REFERENCES:
patent: 4214946 (1980-07-01), Forget et al.
patent: 4570325 (1986-02-01), Higuchi
Kakumu Masakazu
Morita Sigeru
Chaudhuri Olik
Kabushiki Kaisha Toshiba
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