Data demodulator baud clock phase locking

Details Data demodulator baud clock phase locking Data demodulator baud clock phase locking

1988-12-05

1990-04-17

Safourek, Benedict V.

Pulse or digital communications

Repeaters

Testing

375 83, 375119, 329313, H03D 320

Patent

active

049187090

ABSTRACT:
For locking a locally generated baud rate clock signal to the baud rate of a received phase-modulated signal, a multiplifer and measuring circuit produces two quadrature phase bi-level channel signals. In each channel signal the two levels over two given periods which are phased apart by 90.degree. are measured to determine the sign (1=+1, 0=-1) of the channel signals in each of the two periods. A circuit for recovering the timing of the incoming baud rate produces a narrow pulse corresponding to each of the four sign signals thus produced. These pulses are combined into a single continuous pulse sequence. Phase detectors determine the occurrence of successive pairs of the narrow pulses relative to the edge of the local baud clock pulses, and the phase of these clock pulses is adjusted in accordance with the average of the early and late detections.

REFERENCES:
patent: 3971996 (1976-07-01), Motley et al.
patent: 4280224 (1981-07-01), Chethik
patent: 4295222 (1981-10-01), Van Uffelen
patent: 4359692 (1982-11-01), Ryan
patent: 4475217 (1984-10-01), Hughes
patent: 4484337 (1984-11-01), Leclert et al.
patent: 4644566 (1987-02-01), Vercellotti et al.
patent: 4814719 (1989-03-01), Guyer
Lindsey & Chie, A Survey of Digital Phase-Locked Loops, Proceedings of the IEEE, vol. 69, No. 4, Apr. 1981.

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