A method of manufacturing integrated circuits comprising EPROM m

Details A method of manufacturing integrated circuits comprising EPROM m A method of manufacturing integrated circuits comprising EPROM m

1990-01-16

1991-05-07

Hearn, Brian E.

Fishing, trapping, and vermin destroying

437 27, 437 44, 437195, 437 49, 437 52, H01L 21265

Patent

active

050136747

ABSTRACT:
In a process for manufacturing MOS-type integrated circuits which comprise memory floating gate transistors and logic transistors, sandwiches comprising a polysilicon level, an isolation layer, an additional polysilicon level and an additional isolation layer are formed at the position of the memory area. At the position of the logic transistors, the additional polysilicon level is present. An additional isolation layer is deposited on the whole circuit. The substrate is anisotropically etched and there remains in the additional isolation layer, in the memory area, lateral regions which form with the isolation layer an isolating encapsulation around each sandwich and, in the logic transistors area, spacers.

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patent: 4663645 (1987-05-01), Komori et al.
patent: 4764479 (1988-08-01), Kosa et al.
patent: 4775642 (1988-10-01), Chang et al.

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