64-bit single cycle fetch scheme for megastar architecture

Details 64-bit single cycle fetch scheme for megastar architecture 64-bit single cycle fetch scheme for megastar architecture

2005-07-12

2005-07-12

Chace, Chirstian P. (Department: 2187)

Electrical computers and digital processing systems: memory

Storage accessing and control

Control technique

C711S167000, C365S220000, C712S206000

Reexamination Certificate

active

06918018

ABSTRACT:
The 64-bit single cycle fetch method described here relates to a specific ‘megastar’ core processor employed in a range of new digital signal processor devices. The ‘megastar’ core incorporates 32-bit memory blocks arranged into separate entities or banks. Because the parent CPU has only three 16-bit buses, a maximum read in one clock cycle through the memory interface would normally be 48-bits. This invention describes an approach for a fetch method involving tapping into the memory bank data at an earlier stage prior to the memory interface. This allows the normal 48-bit fetch to be extended to 64-bits as required for full performance of the numerical processor accelerator and other speed critical operations and functions.

REFERENCES:
patent: 6240046 (2001-05-01), Proebsting
patent: 2003/0005261 (2003-01-01), Sheaffer
patent: 2004/0073591 (2004-04-01), Giacalone

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