5V tolerant I/O buffer

Details 5V tolerant I/O buffer 5V tolerant I/O buffer

1998-02-02

2000-03-28

Santamauro, Jon

Electronic digital logic circuitry

Interface

Supply voltage level shifting

326 86, 326 57, H03K 1716, H03K 190185

Patent

active

060436808

ABSTRACT:
A circuit and a method are disclosed to provide a tristate input/output buffer which is compatible with 5 volt input signals, applied to its output node, while operating with a 3 volt power supply. This is achieved by inserting an extra p-channel transistor in series with the existing p-channel transistor. The extra p-channel transistor and its parasitic diode are wired so that they will not conduct, i.e. the extra transistor is off and the parasitic diode is back-biased, when a 5 volt input signal is applied to the output of the tristate input/output buffer. Two additional transistors are used to control the on/off state of the extra p-channel transistor.

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patent: 5684415 (1997-11-01), MaManus
patent: 5736869 (1998-04-01), Wei

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