Electronic digital logic circuitry – Interface – Supply voltage level shifting
Reexamination Certificate
2000-12-04
2002-05-21
Tokar, Michael (Department: 2819)
Electronic digital logic circuitry
Interface
Supply voltage level shifting
C326S083000, C326S034000
Reexamination Certificate
active
06392440
ABSTRACT:
BACKGROUND OF THE INVENTION
Field of the Invention
The invention relates to a logic gate with at least one input terminal, at which an input signal is present in two possible logic signal values, and with at least one output terminal for outputting an output signal with a logic signal value. The two possible logic signal values of the output signal are assigned two different logic voltage levels (HIGH, LOW). The configuration further has a logic circuit, which is provided between the input and output terminals and a plurality of switching elements, in particular switching transistors, which are produced or operate according to the logic voltage levels. The logic circuit is supplied by a supply potential that exceeds the logic voltage levels.
Logic gates are the elementary basic building blocks of digital circuits and systems. They control the signal flow through the entire system. The designation gate indicates that they can be opened and closed by the signals present at the input and, in this way, either pass the information on or prevent it from being passed on. Elements appertaining to two-value (binary) logic are considered below, the two logic signal values 0 and 1 being differentiated by the two different voltage levels H or HIGH (typically 3.3 V or 5 V) and L or LOW (typically 0.2 V up to about 1.4 V).
In digital CMOS circuitry, so-called transmission gates (T-gates for short) are widespread in addition to the usual basic gates such as inverters, NAND, NOR and complex gates. The term pass transistor logic also crops up occasionally in this context. This involves a transistor pair consisting of an N-MOS and a P-MOS transistor which are connected in parallel and driven inversely at their gates. As a rule, a T-gate thus comprises two paths, an N-channel transistor path, which can switch through low to medium potentials, and a P-channel transistor path, which can switch through medium to high potentials. In the case of the T-gates known heretofore, each of these paths consists of just one transistor. In one case, both transistors are turned off and constitute an extremely high resistance between their two terminals. In the other case, a conductive connection with a finite resistance is produced between the terminals. A T-gate thus operates like a switch but with the limitation that only voltage potentials lying within the operating voltage of the T-gate can be switched.
The customary operating voltage for the HIGH level has been 5 V for many years. That operating voltage can no longer be adhered to in modern CMOS processes since the transistors have become so small that the physical limit of the maximum field strength is exceeded at 5 V. This is the reason why nowadays there are already many integrated circuits which operate internally with an operating voltage for the HIGH level that has been reduced to 3.3 V. For reasons of compatibility, however, externally the circuits still operate predominantly with 5 V signals. Therefore, level converters are necessary at the interface between the digital circuit and the outside world (that is generally the pad driver circuit). In the case of analog circuits, that means that T-gates have to establish the connection to the outside world. To ensure that the full swing of the analog signals of 5 V can be utilized, circuitry measures must be implemented to construct a T-gate in such a way that no voltages of 5 V occur at the 3.3 V switching transistors of the digital circuit which are to be driven. Otherwise, the service life of the transistors produced using 3.3 V processes would be considerably reduced.
Up to now there have been known only implementations in purely digital circuits which operate with 3.3 V internally and with 5 V externally. Chandrakasan, Burstein, and Brodersen, in “A Low-Power Chipset for a Portable Multimedia I/O Terminal”, IEEE J. of Solid-State Circuits, Vol. 29, No. 12, pp. 1415-28, December 1994, describe a circuit which amplifies 1.1 V signals to the external 5 V swing. The technology thereby used is 5 V compliant.
Pelgrom and Dijkmans, in “A 3/5 volt compatible I/O buffer”, Proc. ESSCIRC, p. 140-43, Ulm 1994, describe a bi-directional circuit using 3.3 V technology which operates with 3.3 V internally and permits external signals of up to 5 V.
Both the aforementioned cases involve level converters which establish the connection between two circuit environments with different operating voltages. A 5 V compliant T-gate and the drive logic required therefor using 3.3 V technology have not been disclosed heretofore.
SUMMARY OF THE INVENTION
The object of the invention is to provide a logic gate circuit which overcomes the above-noted deficiencies and disadvantages of the prior art devices and methods of this kind, and which can perform the function of a T-gate and is constructed in such a way that 5 V signals can be switched without a transistor being operated with impermissibly high voltages.
With the above and other objects in view there is provided, in accordance with the invention, a logic gate, comprising:
an input terminal for receiving an input signal with two possible logic signal values;
an output terminal for outputting an output signal with two possible logic signal values assigned two different logic voltage levels;
a logic circuit connected between the input terminal and the output terminal and supplied by a supply potential exceeding the logic voltage levels;
the logic circuit having a plurality of switching elements, such as switching transistors, configured to operate according to the logic voltage levels, the logic circuit having an output path connected to the output terminal, the output path having at least two switching elements configured to operate according to the logic voltage levels, connected in series, and acting as a voltage divider.
In other words, the invention provides a logic gate circuit having at least one input terminal, at which an input signal is present in two possible logic signal values, and having at least one output terminal for outputting an output signal with a logic signal value, the two possible logic signal values of the output signal being assigned two different logic voltage levels and having a logic circuit, which is provided between the input and output terminals and has a plurality of switching elements, in particular switching transistors, which are produced or operate according to the logic voltage levels, which logic circuit is supplied by a supply potential exceeding the logic voltage levels, in which case the logic circuit has, in its output path assigned to the output terminal, at least two switching elements, in particular switching transistors, which are connected in series and act as a voltage divider.
In accordance with an added feature of the invention, the logic circuit has output path has two reciprocally operating output paths (pull-up path and pull-down path) with switching elements constructed and operating complementarily with respect to one another.
The two output paths may expediently be constructed symmetrically with respect to one another with the output terminal as the point of symmetry.
An essential advantage of the arrangement according to the invention is that a T-gate constructed in such a way can switch higher voltages than a conventional T-gate with the same dielectric strength of the individual transistors. The invention makes it possible to use 3.3 V manufacturing technology to construct 5 V CMOS logic which is suitable for driving T-gates according to the invention which are able to switch (analog) signals with a voltage swing of 5 V.
In accordance with a preferred embodiment of the invention, a CMOS inverter may be provided for driving the T-gate, which inverter can process 5 V signals at the input and once again supplies the full 5 V swing at the output. This circuit is also designed in such a way that the voltage across the transistors always remains distinctly below 5 V. By means of suitable extension, a NAND or a NOR gate and the like may be constructed from the inverter. The combination of the these two extensions can, finall
Chang Daniel D.
Greenberg Laurence A.
Infineon - Technologies AG
Lerner Herbert L.
Stemer Werner H.
LandOfFree
5V compliant transmission gate and the drive logic using... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with 5V compliant transmission gate and the drive logic using..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and 5V compliant transmission gate and the drive logic using... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-2846459