48-bit wide memory architecture addressing scheme reconfigurable

Details 48-bit wide memory architecture addressing scheme reconfigurable 48-bit wide memory architecture addressing scheme reconfigurable

1996-01-11

1999-01-12

Chan, Eddie P.

Electrical computers and digital processing systems: memory

Addressing combined with specific memory configuration or...

395509, 395516, G06F 1204

Patent

active

058600760

ABSTRACT:
A memory addressing method and system is disclosed. In a preferred embodiment, a 48-bit wide memory array is provided wherein eight, 32-bit groups of data are addressable at six (6) memory address locations. Six of the eight 32-bit data groups are addressable at the six memory address locations, while the remaining two 32-bit groups are addressable at aligned, memory address pairs. No page break will occur across the memory address pairs. The contents of the memory are accessed through linear and contiguous addressing. No divide by three operation is required.

REFERENCES:
patent: 4868740 (1989-09-01), Kagimasa et al.
patent: 5396608 (1995-03-01), Garde
patent: 5559969 (1996-09-01), Jennings

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