Electric lamp and discharge devices: systems – Plural power supplies – Plural cathode and/or anode load device
Reexamination Certificate
2001-02-08
2002-04-30
Philogene, Haissa (Department: 2821)
Electric lamp and discharge devices: systems
Plural power supplies
Plural cathode and/or anode load device
C315S169100, C345S068000, C345S080000, C313S581000
Reexamination Certificate
active
06380691
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a plasma display panel, and more particularly, to a surface-discharge alternating-current plasma display panel, a drive method and apparatus therefor.
2. Description of the Related Art
FIG. 1
shows a general three-electrode surface-discharge alternating-current plasma display panel. Address electrode lines A
R1
, A
G1
, . . . , A
Gm
, A
Bm
, dielectric layers
11
and
15
, Y electrode lines Y
1
, . . . , Y
n
, X electrode lines X
1
, . . . , X
n
, a phosphor layer
16
, barrier ribs
17
and a MgO protective film
12
are provided between front and rear glass substrates
10
and
13
of a general surface-discharge plasma display panel
1
.
The address electrode lines A
R1
, A
G1
, . . . , A
Gm
, A
Bm
are formed on the front surface of the rear glass substrate
13
in a predetermined pattern. The dielectric layer
15
is entirely formed in front of the address electrode lines A
R1
, A
G1
, . . . , A
Gm
, A
Bm
, so as to cover the address electrodes A
R1
, A
G1
, . . . , A
Gm
, A
Bm
. The barrier ribs
17
are formed in front of the dielectric layer
15
to be parallel with the address electrode lines A
R1
, A
G1
, . . . , A
Gm
, A
Bm
. The partition walls formed by the barrier ribs
17
define discharge areas of the respective discharge cells and prevent cross talk between each of the respective discharge cells. The phosphor layers
16
are formed between the barrier ribs
17
.
The X electrode lines X
1
, . . . , X
n
and the Y electrode lines Y
1
, . . . , Y
n
, are formed on the rear surface of the front glass substrate
10
in a predetermined pattern to be perpendicular to the address electrode lines AR
1
, A
G1
, . . . , A
Gm
, A
Bm
. The respective intersections define corresponding pixels. The MgO protective film
12
for protecting the plasma display panel
1
against a strong electric field is formed on the rear surface of the dielectric layer
11
. A gas for forming plasma is hermetically sealed in a discharge space
14
.
FIGS. 2A-2E
show driving signals applied to the plasma display panel
1
shown in FIG.
1
. Specifically, S
A
(
FIG. 2A
) denotes driving signals applied to the respective address electrode lines (A
R1
, A
G
1
, . . . , A
Gm
, A
Bm
of FIG.
1
), S
x
(
FIG. 2B
) denotes driving signals applied to the X electrode lines (X
1
, . . . , X
n
of FIG.
1
), and S
Y1
, . . . , S
Yn
(
FIGS. 2C-2E
) denote driving signals applied to the Y electrode lines (Y
1
, . . . , Y
n
of FIG.
1
), respectively. An address period A
1
in a unit subfield SF
1
is divided into reset periods A
11
, A
12
and A
13
and a main address period A
14
.
During a display discharge period S
1
, a common pulse of a voltage V
S
, which is higher than a positive voltage V
XB
, is alternately applied to all of Y electrode lines Y
1
, . . . , Y
n
and the X electrode lines X
1
, . . . , X
n
so that display discharges occur at discharge cells where wall charges were formed during the corresponding address period A
1
. In the case where the last pulse is applied to the X electrode lines X
1
, . . . , X
n
during the display discharge period S
1
, electrons are formed in the vicinity of the X electrode lines of selected displayed discharge cells and positive charges are formed in the vicinity of Y electrode lines. Accordingly, during the first reset period A
11
, a voltage V
RX
lower than the positive voltage V
XB
is applied to the X electrode lines X
1
, . . . , X
n
, thereby performing a discharge in which the wall charges are primarily erased. Also, during the second reset period A
12
, a narrow-width voltage of the V
S
is applied to the Y electrode lines Y
1
, . . . , Y
n
, thereby performing a discharge in which the remaining wall charges are secondarily erased. Finally, during the third reset period A
13
, the voltage V
RX
is again applied to the X electrode lines X
1
, . . . , X
n
, thereby performing a discharge in which the wall charges are finally erased. Accordingly, all of the wall charges can be erased from the discharge space, and space charges can be uniformly distributed throughout the discharge space.
During the main address period A
14
, display data signals are applied to the address electrode lines A
R1
, A
G1
, . . . , A
Gm
, A
Bm
, and simultaneously the corresponding scan pulses are sequentially applied to the Y electrode lines Y
1
, . . . , Y
n
. The display data signals applied to the address electrode lines A
R1
, A
G
1
, . . . , A
Gm
, A
Bm
are a positive voltage Va in the case where a discharge cell is selected, and a ground voltage, i.e., 0 volts, in the case where a discharge cell is not selected. A bias voltage V
RX
is applied to the respective Y electrode lines Y
1
, . . . , Y
n
during a scanning time, and 0 volts are applied thereto during a non-scanning time. Accordingly, if a display data signal of Va is applied while a scan pulse of 0 volts is applied, wall charges are formed by address discharge at the corresponding discharge cell. Otherwise, wall charges are not formed at the other discharge cells. Here, for more accurate and effective address discharge, a voltage V
XB
lower than V
S
and higher than V
YB
is applied to the X electrode lines X
1
, . . . , X
n
.
FIG. 3
shows a driving apparatus for generating the driving signals shown in
FIGS. 2A-2E
. The driving apparatus of the conventional 3-electrode plasma display panel
1
includes a controller
32
, an address driver
33
, an X driver
34
and a Y driver
35
. The controller
32
generates driving control signals S
CA
, S
CY
and S
CX
in accordance with a video signal externally applied. The address driver
33
processes the address driving control signal S
CA
among the driving control signals S
CA
, S
CY
and S
CX
generated by the controller
32
to generate a display data signal (S
A
of FIG.
2
A), and applies the generated display data signal S
A
to the address electrode lines A
R1
, A
G1
, . . . , A
Gm
, A
Bm
. The X driver
34
processes the X driving control signal SCX among the driving control signals S
CA
, S
CY
and S
CX
generated by the controller
32
to generate an X driving signal (S
X
FIG.
2
B), and applies the generated X driving signal S
X
to the X electrode lines X
1
, . . . , X
n
.
The Y driver
35
processes the Y driving control signal S
CY
among the driving control signals S
CA
, S
CY
and S
CX
generated by the controller
32
to generate Y driving signals (S
Y1
, S
Y2
. . . , S
Yn
of FIGS.
2
C-E), and applies the same to the Y electrode lines Y
1
, . . . , Y
n
. The Y driver
35
is divided into a scan driver
351
and a Y-common driver
352
. The scan driver
351
outputs its driving signals during an address period (A
1
of
FIGS. 2A-E
) only, and the Y-common driver
352
outputs its driving signals during the display discharge period (S
1
) only. The Y electrode lines Y
1
, . . . , Y
n
of the conventional 3-electrode plasma display panel
1
must be driven during the display discharge period S
1
as well as the address period A
1
. Thus, the respective output ports of the Y-common driver
352
must be connected with the corresponding output ports of the scan driver
351
. Also, in order to uniformly control the respective driving timings by switching, the unit circuits of the Y-common driver
352
and the scan driver
351
for driving the Y electrode lines Y
1
, . . . , Y
n
must be connected to each other. Therefore, the Y-common driver
352
and the scan driver
351
require many components. Also, many elements are required for separating or switching the Y-common driver
352
and the scan driver
351
. Thus, the scan driver
351
of the conventional driving apparatus consumes much power and emits a large amount of heat.
A driving apparatus of a plasma display panel consuming a high amount of power must have power regeneration circuits. The power regeneration circuits are provided in the Y-common driver
352
and the X driver
34
. In other words, in the display discharge period (S
1
of FIGS.
2
A-E), the Y-common driver
352
and the X-driver
34
w
Philogene Haissa
Samsung SDI & Co., Ltd.
Staas & Halsey , LLP
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