3D silicon-silicon die stack structure and method for fine...

Details 3D silicon-silicon die stack structure and method for fine... 3D silicon-silicon die stack structure and method for fine...

2009-08-18

2011-11-01

Louie, Wai Sing (Department: 2814)

Semiconductor device manufacturing: process

Coating with electrically or thermally conductive material

To form ohmic contact to semiconductive material

C257S774000, C438S613000, C438S614000, C438S615000, C438S616000, C438S617000, C438S015000, C438S017000, C438S018000

Reexamination Certificate

active

08048794

ABSTRACT:
A method of fabricating a thin wafer die includes creating circuits and front-end-of-line wiring on a silicon wafer, drilling holes in a topside of the wafer, depositing an insulator on the drilled holes surface to provide a dielectric insulator, removing any excess surface deposition from the surface, putting a metal fill into the holes to form through-silicon-vias (TSV), creating back-end-of-line wiring and pads on the top surface for interconnection, thinning down the wafer to expose the insulator in from the TSVs to adapt the TSVs to be contacted from a backside of the wafer, depositing an insulating layer which contacts the TSV dielectric, thinning down the backside of the wafer, opening through the dielectric to expose the conductor of the TSV to provide a dielectric insulation about exposed backside silicon, and depositing ball limiting metallurgy pads and solder bumps on the backside of the wafer to form an integrated circuit.

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