3D integrated circuits using thick metal for backside...

Details 3D integrated circuits using thick metal for backside... 3D integrated circuits using thick metal for backside...

2005-11-21

2008-08-12

Sarkar, Asok K (Department: 2891)

Semiconductor device manufacturing: process

Bonding of plural semiconductor substrates

C438S107000, C438S459000, C257S686000, C257SE25006, C257SE21614

Reexamination Certificate

active

07410884

ABSTRACT:
Backside connections for 3D integrated circuits and methods to fabricate thereof are described. A stack of a first wafer over a second wafer that has a substrate of the first wafer on top of the stack, is formed. The substrate of the first wafer is thinned. A first dielectric layer is deposited on the thinned substrate. First vias extending through the substrate to the first wafer are formed in the first dielectric layer. A conductive layer is deposited in the first vias and on the first dielectric layer to form thick conductive lines. Second dielectric layer is formed on the conductive layer. Second vias extending to the conductive lines are formed in the second dielectric layer. Conductive bumps extending into the second vias and offsetting the first vias are formed on the second dielectric layer.

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