3D channel architecture for semiconductor devices

Details 3D channel architecture for semiconductor devices 3D channel architecture for semiconductor devices

2009-06-08

2011-12-06

Jackson, Jr., Jerome (Department: 2815)

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

C257S341000, C257SE29257, C257SE29260

Reexamination Certificate

active

08072027

ABSTRACT:
Semiconductor devices and methods for making such devices that contain a 3D channel architecture are described. The 3D channel architecture is formed using a dual trench structure containing with a plurality of lower trenches extending in an x and y directional channels and separated by a mesa and an upper trench extending in a y direction and located in an upper portion of the substrate proximate a source region. Thus, smaller pillar trenches are formed within the main line-shaped trench. Such an architecture generates additional channel regions which are aligned substantially perpendicular to the conventional line-shaped channels. The channel regions, both conventional and perpendicular, are electrically connected by their corner and top regions to produce higher current flow in all three dimensions. With such a configuration, higher channel density, a stronger inversion layer, and a more uniform threshold distribution can be obtained for the semiconductor device. Other embodiments are described.

REFERENCES:
patent: 4379305 (1983-04-01), Mitchell
patent: 4673962 (1987-06-01), Chatterjee
patent: 5072266 (1991-12-01), Bulucea
patent: 5326711 (1994-07-01), Malhi
patent: 5567635 (1996-10-01), Acovic et al.
patent: 5670803 (1997-09-01), Beilstein, Jr. et al.
patent: 6037202 (2000-03-01), Witek
patent: 6066878 (2000-05-01), Neilson
patent: 6207994 (2001-03-01), Rumennik
patent: 6271562 (2001-08-01), Deboy et al.
patent: 6281547 (2001-08-01), So et al.
patent: 6384456 (2002-05-01), Tihanyi
patent: 6710403 (2004-03-01), Sapp
patent: 2001/0050394 (2001-12-01), Onishi et al.
patent: 2005/0017293 (2005-01-01), Zundel et al.
patent: 2007/0158701 (2007-07-01), Chang
patent: 2007/0173021 (2007-07-01), Kocon et al.
patent: 2008/0090339 (2008-04-01), Herrick
patent: 2008/0258213 (2008-10-01), Yilmaz
patent: 2008/0258237 (2008-10-01), Kim
patent: PCT/US2010/037656 (2010-06-01), None

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