Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital data error correction
Reexamination Certificate
1998-05-29
2001-04-10
Moise, Emmanuel L. (Department: 2133)
Error detection/correction and fault detection/recovery
Pulse or data error handling
Digital data error correction
C714S042000, C714S768000
Reexamination Certificate
active
06216247
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The invention relates generally to computer systems design and development. More specifically, the invention relates to the design of memories and memory subsystems for use in computer systems.
2. Description of the Related Art
In servers and systems that are not by nature servers, but operate in a server capacity, reliability has often been the controlling issue. Now, with increased load by more complex applications and more numerous client base, performance has also become an issue. To solve the performance problem in servers, separate intelligent I/O (Input/Output) systems have been developed which specifically address certain specific performance and reliability issues with regard to various server functions. Intelligent I/O includes the use of an I/O processor (IOP) separate from the host processor which performs many of the I/O functions of the computer system so that the host processor is freed from the incessant slowdown due I/O interrupts and other mechanisms which burden applications running on the host processor.
Two I/O functions that may be offloaded to the IOP include the RAID (Redundant Array of Inexpensive Disks) algorithm and networking packet assembly and disassembly. To handle these and other functions, the IOP is always accompanied by a local memory. For instance, such a local memory could act as the disk cache upon which the parity image for the RAID algorithm is stored and updated. The I/O subsystem's local memory must be designed such that it minimizes latency and can handle the throughput required for various applications. Further, the memory configuration is best if utilizing standard readily available memory components so that the cost is not increased by the need to introduce special size/configuration memory components into the system.
Due to the differences in what is required from the local I/O memory, however, it is often impossible to choose a configuration of memory that will be optimal for all potential I/O functions. Specifically in this regard, the use of memories equipped with Error Correction Code (ECC) mechanisms demands certain specific design constraints. ECC-capable memory is utilized since it allows for the detecting of double bit errors (two bits are incorrect within a transfer block) and for correcting a single bit error, and thus provides improved reliability over parity memory (which has the capability of detecting but not correcting single bit errors and no capability with regard to double bit errors). ECC however is currently implemented for systems that have 64-bit wide data busses. Sixty-four-bit ECC uses operations such as hashing to generate an 8-bit value which may help detect an error for the 64 bits in each data block. Thus, the entire memory bus would have a bandwidth of 72 bits, which, being a multiple of 4, may be readily assembled since memory modules are currently manufactured as in widths of 4, 8, 16 and 32 bits.
However, having a 64-bit architecture may impose a burden upon I/O functions that prefer a lower cost over performance. To have the reliability advantage of ECC and the optimization of 32-bit architectures useful for certain I/O functions, it would be desirable to generate the hamming code for 32-bit data. By definition, a hamming code generated for 32 bits of data is less than 6 bits wide. Thus, a total memory width of N bits, where N is not a multiple of 8 or 4 would be needed. This is inconvenient to assemble since N is not a multiple of 4 or 8. In certain I/O processors that desire a 32-bit implementation as well as a hamming code, it would be advantageous to still generate an 8-bit hamming code so that both 64 bit and 32 bit data busses can be supported by the memory architecture. The 40 bits resultant from 32-bit data and an 8-bit Hamming code would allow for convenient assemblage since 40-bit memory modules are industry standards. Further, in intelligent I/O systems where both a 32-bit mode and 64-bit mode are available (so that design is more flexible based on the I/O function), it would be desirable to have ECC reliability without increasing the complexity of the addressing implicit in each mode.
SUMMARY OF THE INVENTION
What is disclosed is a method that includes placing a memory subsystem into a first mode, the memory subsystem operating previously in a second mode, the first mode indicative of a first data block transfer size, the second mode indicative of a second data block transfer size, the second size larger than the first size, and transacting a data block with the memory subsystem in the first mode, the transacting performed with error correction code capability in either of the modes.
REFERENCES:
patent: 4201337 (1980-05-01), Lewis et al.
patent: 5481552 (1996-01-01), Aldereguia et al.
patent: 5555250 (1996-09-01), Walker et al.
patent: 5835704 (1998-10-01), Li et al.
Creta Kenneth C.
Garbus Elliot
Blakely , Sokoloff, Taylor & Zafman LLP
Intel Corporation
Moise Emmanuel L.
LandOfFree
32-bit mode for a 64-bit ECC capable memory subsystem does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with 32-bit mode for a 64-bit ECC capable memory subsystem, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and 32-bit mode for a 64-bit ECC capable memory subsystem will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-2471896