32 bit generic bus interface using read/write byte enables

Electrical computers and digital data processing systems: input/ – Intrasystem connection – Bus interface architecture

Reexamination Certificate

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Details

C710S306000

Reexamination Certificate

active

06904486

ABSTRACT:
A display controller configured to communicate with a microprocessor is provided. The display controller includes a memory core for storing image data to be displayed and a register set containing configuration data enabling presentation of the image data. A bus interface enabling communication over a bus between the memory core of the display controller and the microprocessor is included. The bus interface is configured to communicate with a set of command signals. The set of command signals defines both whether read operations and write operations are to occur over a bus cycle and whether valid data exists for each bit of the read operation and the write operation. Each command signal in the set of command signals defines enable data for the read operations or write operations. A system including the display controller and methods for adapting the display controller to communicate with a variety of microprocessors are also included.

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