3-state bicmos output buffer having power down capability

Details 3-state bicmos output buffer having power down capability 3-state bicmos output buffer having power down capability

1994-02-14

1996-08-13

Westin, Edward P.

Electronic digital logic circuitry

Interface

Current driving

326 84, 326 58, H03K 190175

Patent

active

055460216

ABSTRACT:
A 3 state BiCMOS output buffer (100) with power down capability has been provided. The buffer includes an input stage (102), responsive to an input signal, an output coupled to both a pull-up driver (114), and an output pull-down driver (116) wherein the drivers provide an output signal at an output of the buffer in response to the input signal. Additionally, the buffer includes a power down sense circuit (108), coupled to a power supply node (118), for turning off an output pull-up transistor (214) when the power supply node is powered down and thus eliminating leakage paths within the buffer. The buffer also includes a noise limiting circuit (112) for slowing down a high to low transition at the output of the buffer thereby reducing the switching noise of the buffer while not affecting the overall speed of the buffer.

REFERENCES:
patent: 5153457 (1992-10-01), Martin et al.
patent: 5223745 (1993-06-01), Ohannes et al.
patent: 5231311 (1993-07-01), Ferry et al.
patent: 5256914 (1993-10-01), Boomer
patent: 5266849 (1993-11-01), Kitahara et al.
patent: 5276364 (1994-01-01), Wellheuser
patent: 5338978 (1994-08-01), Larsen et al.
Fletcher et al. Sep. 1990. "Bicmos Futurebus Transceiver" IEEE International Conference On Computer Design. pp. 11-13.
E. Schoppnies. 1991. "Bicmos Fur Die Zukunft" Radio Fernsehen Elektronik. vol. 40. No. 3/4, p. 154.

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