3-dimensional flash memory device, method of fabrication and...

Active solid-state devices (e.g. – transistors – solid-state diode – Combined with electrical contact or lead – Chip mounted on chip

Reexamination Certificate

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Details

C438S109000, C257SE21614, C257SE25006

Reexamination Certificate

active

07960844

ABSTRACT:
Disclosed are a flash memory device and method of operation. The flash memory device includes a bottom memory cell array and a top memory cell array disposed over the bottom memory cell array. The bottom memory cell array includes a bottom semiconductor layer, a bottom well, and a plurality of bottom memory cell units. The top memory cell array includes a top semiconductor layer, a top well, and a plurality of top memory cell units. A well bias line is disposed over the top memory cell array and includes a bottom well bias line and a top well bias line, The bottom well bias line is electrically connected to the bottom well, and the top well bias line is electrically connected to the top well.

REFERENCES:
patent: 6541324 (2003-04-01), Wang
patent: 7271451 (2007-09-01), Liaw
patent: 7355885 (2008-04-01), Fukuzumi
patent: 2007/0200182 (2007-08-01), Liaw
patent: 2006019735 (2006-01-01), None
patent: 100230426 (1999-08-01), None
patent: 100687051 (2007-02-01), None
patent: 1020080035799 (2008-04-01), None
patent: 100829611 (2008-05-01), None

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