3-D integrated circuit assembly employing discrete chips

Details 3-D integrated circuit assembly employing discrete chips 3-D integrated circuit assembly employing discrete chips

1989-08-31

1991-07-16

Hille, Rolf

Electricity: electrical systems and devices

Safety and protection of systems and devices

With specific current responsive fault sensor

357 71, 357 80, 361420, 361416, 361413, H01L 2316, H01L 3902, H01L 2548, H01L 2946

Patent

active

050328964

ABSTRACT:
A 3-D IC chip assembly is formed from stacked substrates in which each individual substrate has a plurality of different IC chips retained in respective recesses. Conductive feedthroughs extend through the substrate from the side where the chips are located to the opposite side, with the chips electrically connected to the feedthroughs. An electrical routing network on the opposite side of the substrate from the chips provides desired interconnections between the chips by connecting to the feedthroughs. The routing can be formed by standard photolithographic techniques.

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R. O. Carlson et al, "A High Density Copper/Polyimide Overlay Interconnection", Eighth International Electronics Packaging Conference, Nov. 7-10, 1988.
"GE Method overcomes previous wafer-scale integration problems", E. J. Lerner, Research & Development Magazine, 10/85, pp. 51-52.
"High Density Overlay for Bare Chip Interconnect", J. E. Kohl, 1988 GOMAC Proceedings, pp. 445-448.

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