3-D column select circuit layout in semiconductor memory...

Details 3-D column select circuit layout in semiconductor memory... 3-D column select circuit layout in semiconductor memory...

2007-05-08

2007-05-08

Prenty, Mark V. (Department: 2822)

Active solid-state devices (e.g., transistors, solid-state diode

Non-single crystal, or recrystallized, semiconductor...

Field effect device in non-single crystal, or...

C257S074000, C257S351000, C257S903000

Reexamination Certificate

active

11206437

ABSTRACT:
A column select circuit in a Static Random Access Memory (SRAM) having a three-dimensional layout can include a lower CMOS layer in a substrate and an upper NMOS layer above the lower layer. An intermediate PMOS layer is located between the upper NMOS layer and the lower CMOS layer.

REFERENCES:
patent: 5525814 (1996-06-01), Malhi
patent: 2001/0050442 (2001-12-01), Lee
patent: 2004/0007746 (2004-01-01), Zhang

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