3-D CMOS transistors with high ESD reliability

Details 3-D CMOS transistors with high ESD reliability 3-D CMOS transistors with high ESD reliability

1998-04-20

2000-09-19

Prenty, Mark V.

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

257351, 257 69, H01L 2976

Patent

active

061216623

ABSTRACT:
The present invention discloses a structure for 3-D transistors with high electrostatic discharge (ESD) reliability. The 3-D transistors are fabricated on a substrate. The substrate has several recess portions and silicon islands. Several buried oxide regions are formed in the silicon islands and upper portions of the silicon islands are isolated from the substrate by the buried oxide regions. Then, a gate oxide layer is formed on the substrate. The upper portions of the silicon islands are enclosed by the gate oxide layer and the buried oxide region. A gate structure is defined on each of the recess portions and silicon islands. Two N-type source/drain regions are defined in each of the silicon islands adjacent to each of the gates on the silicon islands. Two P-type source/draid regions are fabricated in each of the recess portions adjacent to each of the gates on the recess portion. Spacers are defined on the sidewalls of the gates and abutting to the gates. Therefore, PMOS transistors are fabricated on silicon-on-insulator regions and NMOS transistors are defined on the recess portions of the substrate.

REFERENCES:
patent: 4754314 (1988-06-01), Scott et al.
patent: 5326991 (1994-07-01), Takasu
patent: 5847419 (1998-12-01), Imai et al.
patent: 5869872 (1999-02-01), Asai et al.
patent: 5886385 (1999-03-01), Arisumi et al.

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