Electronic digital logic circuitry – Interface – Supply voltage level shifting
Patent
1994-09-22
1995-11-14
Westin, Edward P.
Electronic digital logic circuitry
Interface
Supply voltage level shifting
326 27, 326 58, 327534, H03K 190175
Patent
active
054670314
ABSTRACT:
A CMOS tri-state driver circuit is capable of operating in a normal drive mode and in a high impedance mode. The circuit is powered by a 3 volt power supply, and drives an output terminal that is common to a TTL or other device that can apply a 5 volt output to the output terminal. The circuit includes a PMOS pull-up transistor and an NMOS pull-down transistor that are connected to the output terminal. The pull-up transistor is formed in and has a substrate terminal that is connected to an N-well. A switching transistor is controlled to connect the N-well to the power supply in drive mode to ensure stable and strong pull-up drive. A pass-gate transistor is biased to turn off the switching transistor when the voltage at the output terminal is higher than the power supply voltage in high impedance mode, causing the N-well to float. This prevents leakage current from flowing through a semiconductor junction from the output terminal to the N-well through the pull-up transistor. A shorting transistor is controlled to short the gate of the pull-up transistor to the N-well when the voltage at the output terminal is higher than the power supply voltage in high impedance mode, thereby preventing leakage current from flowing through the channel of the pull-up transistor.
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Martin, Brian C.; Tips for Straddling the 3-V to 5V Fence; Electronic Design; Apr. 4, 1994, pp. 67-73.
Luong Hung
Nguyen Trung
LSI Logic Corporation
Sanders Andrew
Westin Edward P.
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