3.3 V to 5 V supply interface buffer

Details 3.3 V to 5 V supply interface buffer 3.3 V to 5 V supply interface buffer

1993-09-24

1995-04-25

Hudspeth, David R.

Electronic digital logic circuitry

Interface

Supply voltage level shifting

326 83, H03K 190175, H03K 19094

Patent

active

054102677

ABSTRACT:
An improved 3.3 V to 5 V interface buffer comprising a solid state BiCMOS device implemented on a reduced voltage process designed to operate from 3.3 V and 5 V supplies and capable of receiving a 0-3.3 V input signal while providing a external swing signal from 0-5 V. Specifically, cross coupled PMOS and NMOS devices manufactured by a 3.3 V process are utilized with level shifting diodes for achieving a device which operates on higher voltages than conventional circuit design techniques allow for a given process technique, while providing a 0-5 V output at the sending device.

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Takahashi, Makoto, Saukrai, Takayasu, Sawada, Kazuhiro, Nogami, Kazutaka, Ichida, Makoto and Matsuda, Koji, Titled "3.3V-5V Compatible I/O Circuit without Thick Gate Oxide", Proceedings of the IEEE 1992 Custom Integrated Circuits Conference, 1992 IEEE, pp. 23.3.1-23.3.4.
DeClercq, Michel J., Schubert, Martin, and Clement, Francois, Titled "TP10.6: 5V-to-75V CMOS Output Interface Circuits", 1993 IEEE International Solid-State Circuits Conference Digest of Technical Papers, Publisher John H. Wuorinen, First Edition, Feb. 1993, IEEE Catalog Number 93CH3272-2, pp. 162 and 163.

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