Coded data generation or conversion – Analog to or from digital conversion – Digital to analog conversion
Reexamination Certificate
1999-09-10
2001-07-24
Wamsley, Patrick (Department: 2819)
Coded data generation or conversion
Analog to or from digital conversion
Digital to analog conversion
C341S143000
Reexamination Certificate
active
06266002
ABSTRACT:
BACKGROUND OF THE INVENTION
Delta Sigma (&Dgr;-&Sgr;) Analog-to-Digital converters (ADCs) and digital-to-analog converters (DAC's), collectively referred to as &Dgr;-&Sgr; data converters, are widely used in high-precision, low bandwidth applications, such as digital audio processing. Through the use of oversampling, the data path width can be reduced from, for example sixteen bits to one bit. The resultant quantization noise due to quantizing from sixteen bits to one bit is shaped such that the noise is moved outside of the signal band. The use of the smaller data path facilitates the design of the analog circuit, since a data path of, for example, one bit is the easiest for analog design.
To improve the performance of a &Dgr;-&Sgr; data converter, noise shaping is utilized. By increasing the order of the noise shaping, this inband noise performance can be improved. The primary purpose for utilizing the one bit modulator is the inherent linearity associated therewith, since one bit only requires two levels, requiring a straight line therebetween. The reason for going to a multi-bit modulator is primarily due to the lower out of band noise, which requires less analog circuitry for the filtering thereof. Other advantages are that it a) the modulator is more stable requiring less order with a higher gain factor, b) its inband noise is smaller, and c) there is less output jitter sensitivity since the steps are smaller in the output. Linear performance can only be achieved if the steps between adjacent output levels of each DAC have very nearly the same magnitude. This, therefore, requires a matching precision that is on the order of the desired precision of the overall data converter, and this is often beyond the practical limits of present manufacturing technology.
In order to solve the problem with element matching, various techniques have been utilized such as dynamic element matching in multi-bit noise-shaping DACs. In these techniques, the mismatches are accepted as inevitable, with their negative effects being avoided through signal processing, i.e., an intelligent selection of the DACs that are utilized in the conversion.
SUMMARY OF THE INVENTION
The present invention disclosed and claimed herein comprises a method for converting data which includes the step of first receiving the data to be converted in an associated conversion operation. The data is comprised of a series of data values, each associated with one conversion operation. This data is processed through a multi-bit digital-to-analog conversion operation. In this conversion operation, a plurality of digital-to-analog conversion (DAC) elements are provided, each operable to provide one of a plurality of discrete values therefrom. The discrete values for each of the elements are selected, with these values available for output from each of the DAC elements in accordance with the value being converted in the associated conversion operation. These outputs for each of the DAC elements are then summed for the associated received data and the associated conversion operation. The operation of selecting the discrete values in accordance with the uniform selection algorithm is such that the noise response of the digital-to-analog conversion operation is shaped. The uniform selection algorithm determines the values for each of the DAC elements associated with the conversion operation, accounting for mismatching in the DAC elements. A constraint is placed upon this uniform selection algorithm during the operation thereof to change the values of at least two of the DAC elements from that determined by the uniform selection algorithm. The result of the conversion operation is then output for each of the output conversion cycles.
REFERENCES:
patent: 5684482 (1997-11-01), Galton
patent: 5818377 (1998-10-01), Wieser
patent: 6137430 (2000-10-01), Lyden et al.
Yasuda et al, “A Third Order Delta-Sigma Modulator Using Second-Order Noise Shaping Dynamic Element Matching,” IEEE 1879-1886, Dec. 1998.*
Radke et al, “A Spurious-Free Delta-Sigma DAC Using Rotated Data Weighted Averaging,” IEEE, 125-128, Dec. 1998.*
Spectral Shaping of Circuit Errors in Digital-to-Analog Converters, Ian Galton, IEEE, pp. 808-817, Oct. 1997.
Alexander Mark
Gaalaas Eric
Gong Xue-Mei
Cirrus Logic Inc.
Howison Gregory M.
Lin Steven
Wamsley Patrick
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