2n×n multiplexing switch

Details 2n×n multiplexing switch 2n×n multiplexing switch

1998-05-20

2001-09-11

Olms, Douglas (Department: 2661)

Multiplex communications

Pathfinding or routing

Through a circuit switch

C370S412000, C370S422000

Reexamination Certificate

active

06289011

ABSTRACT:

CLAIM OF PRIORITY
This application makes reference to, incorporates the same herein, and claims all benefits accruing under 35 U.S.C. §119 from an application for 2n×n MULTIPLEXING SWITCH earlier filed in the Korean Industrial Property Office on May 21, 1997 and there duly assigned Ser. No. 19656/1997.
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a 2n×n multiplexing switch used for implementing the Advanced ATM Exchange and particularly relates to a 2n×n multiplexing switch including a VD (Valid) extracting part for generating a VD signal for determining whether or not a cell is to be transmitted, a shared FIFO (First In First Out) buffer selecting device for selecting the shared FIFO buffer, an output device and a cell counter.
2. Description of the Related Art
Up to now the Advanced (large capacity) Switch is implemented using full identical −n×n switches.
The earlier n×n switch used for implementing large capacity switches, includes a port filtering device including n port filters for each port, a FIFO (First In First Out) buffer selecting device, a shared FIFO buffering device including n FIFOs and an output device. Namely, in the past for implementing an n×n switch 2n port filters, n FIFO buffer selecting devices, 2n FIFOs and n output devices were indispensable.
The switch, first of all, copies the input cells n times and respectively transmits them to the port filter for each port. The port filter recognizes whether the cell being inputted is to be transmitted to its port. If the cell being inputted is to be transmitted to its port, the port filter transmits the cell to the FIFO buffer selecting device. If not, the port filter discards the cell.
The FIFO buffer selecting device configures the FIFO address and the transmission line so that the cell which has passed through the port filter can be stored in the shared FIFO buffering device, and the output device reads a cell from the shared FIFO buffering device every cell time and transmits it to the output port.
For implementing the n×n switch as stated above, it has problems in that quite a few steps are required, and the shared FIFO buffering device, which is included correspondingly to each port, cannot be shared, so that the FIFO buffer to need be very large.
Particularly, when a large-capacity switch is to be implemented, it has also problems in that the complete sharing of the output port cannot be easily implemented and for implementing the large-capacity switch, a very large quantity of logic gates are needed.
In addition, there is a problem in that if once the large-capacity switch is implemented using the n×n switch, it has basically the architecture of a Banyan network and in the above case, a degradation to a considerable extent is unavoidable.
The following patents each disclose features in common with the present invention but do not teach or suggest the specifically recited multiplexing switch of the present invention: U.S. Pat. No. 5,745,489 to Diaz et al., entitled Buffered Crosspoint Matrix For An Asynchronous Transfer Mode Switch And Method Of Operation, U.S. Pat. No. 5,724,354 to Tremel et al., entitled Method For The Insertion Of Cells Into An ATM Type Flow And Implementation Device, U.S. Pat. No. 5,684,798 to Gauthier, entitled Communication System Comprising A Network And A Multiplexing Device And Multiplexing Device Suitable For Such A System, U.S. Pat. No. 5,687,172 to Cloonan et al., entitled Terabit Per Second Distribution Network, U.S. Pat. No. 5,724,352 to Cloonan et al., entitled Terabit Per Second Packet Switch Having Assignable Multiple Packet Loss Probabilities, U.S. Pat. No. 5,608,719 to Hyodo et al., entitled ATM Multiplex Transmission System Having Test Equipment, U.S. Pat. No. 5,610,914 to Yamada, entitled Shared Buffer Memory Switch For An ATM Switching System And Its Broadcasting Control Method, U.S. Pat. No. 5,619,510 to Kurano, entitled Output Buffer Type Asynchronous Transfer Mode Switch And Detecting Error Boards Thereof, U.S. Pat. No. 5,642,349 to Cloonan et al., entitled Terabit Per Second ATM Packet Switch Having Distributed Out-Of-Band Control, U.S. Pat. No. 5,577,035 to Hayter et al., entitled Apparatus And Method Of Processing Bandwidth Requirements In An ATM Switch, U.S. Pat. No. 5,383,181 to Aramaki, entitled Packet Switching System Capable Qf Reducing A Delay Time For Each Packet, U.S. Pat. No. 5,406,554 to Parry, entitled Synchronous FIFO Having An Alterable Buffer Store, U.S. Pat. No. 5,448,559 to Hayter et al, entitled ATM Communication System With Interrogation Of Output Port Servers For Available Handing Capacity, U.S. Pat. No. 5,550,823 to Irie et al., entitled Method And Apparatus For Performing Priority Control For Cells In Output Buffer Type ATM Switch, U.S. Pat. No. 5,535,197 to Cotton, entitled Shared Buffer Switching Module, U.S. Pat. No. 5,732,085 to Kim et al., entitled Fixed Length Packet Switching Apparatus Using Multiplexers And Demultiplexers, U.S. Pat. No. 5,732,069 to Nagino et al., entitled ATM Switch, U.S. Pat. No. 5,710,770 to Kozaki et al., entitled ATM Cell Switching System, and U.S. Pat. No. 5,548,588 to Ganmukhi et al., entitled Method And Apparatus For Switching, Multicasting Multiplexing And Demultiplexing An ATM Cell.
SUMMARY OF THE INVENTION
To solve the above described problems, it is the object of the present invention to provide a 2n×2 multiplexing switch, which makes it possible to use n output ports uniformly, and uses a smaller number of path assignment tags as compared to earlier arrangements, and can minimize the diminishment of the efficiency by using a common buffer type switch.
Other objects and benefits of the present invention become apparent, if the following detailed description of the present invention is read and the attached drawings are referenced. A preferable embodiment of a 2n×n multiplexing switch may be constructed according to the principles of the present invention with a VD (valid) extracting device having 2n VD extractors, which validate the routing tags of the inputted cells and determine if the cell is to be saved or not and generates a VD signal; a FIFO buffer selecting device, which selects FIFO buffer to store each cell using said VD signal and transfers each cell to the selected FIFO buffer; a shared FIFO buffering device having 2n shared FIFO buffers and storing cells; an output device, which reads cells stored in the FIFO buffers and transfers n cells to output ports; and a cell counter, which counts cells stored currently in the shared FIFO buffering device using the data from the FIFO buffer selecting device and the output device. In the practice of the present invention, it is preferable that the FIFO buffer selecting device comprises a FIFO buffer address extracting device and a Banyan routing network.
It is preferable that the FIFO buffer address extracing device generates a FIFO address buffer (FAB) using 2n adders and 2n buffers. It is preferable that the adders inputs an FAB read finally at the previous cell time and VD, and if the VD is zero, then one is added, or else zero is added, and the result becomes the input of the next adders and at the same time it is stored in the buffer.
It is preferable that the output device be constructed with a read FIFO buffer address (RFA) generator reading cell count(CCNT); a FIFO buffer read enable (FRE) generator, which inputs the read FIFO buffer address from the read FIFO buffer address generator; and an output cell multiplexing device, which inputs the read FIFO buffer address from the read FIFO buffer address generator and inputs cells from the shared FIFO buffering device.
It is preferable that the read FIFO buffer address generator be constructed with n adders, which add one if the cell count read finally before one cell time is above zero, or else adds zero, and inputs the result to the next adder; and n buffers, which at the same time inputs the values inputted from the adders.
It is preferable that the i
th
adder adds one, if the cell count

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