Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reexamination Certificate
2001-03-08
2004-07-06
Flynn, Nathan J. (Department: 2826)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
C257S314000
Reexamination Certificate
active
06759707
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention relates to the field of semiconductor manufacture and, more particularly, to a 2F
2
flash memory.
As computers become increasingly complex, the need for improved memory storage increases. At the same time, there is a continuing drive to reduce the size of computers and memory devices. Accordingly, a goal of memory device fabrication is to increase the number of memory cells per unit area.
Memory devices contain blocks or arrays of memory cells. A memory cell stores one bit of information. Bits are commonly represented by the binary digits 0 and 1. A flash memory device is a non-volatile semiconductor memory device in which contents in a single cell or a block of memory cells are electrically programmable and may be read or written in a single operation. Flash memory devices have the characteristics of low power and fast operation making them ideal for portable devices. Flash memory is commonly used in portable devices such as laptop or notebook computers, digital audio players and personal digital assistant (PDA) devices.
In flash memory, a charged floating gate is one logic state, typically represented by the binary digit 1, while a non-charged floating gate is the opposite logic state typically represented by the binary digit 0. Charges are injected or written to a floating gate by any number of methods, including avalanche injection, channel injection, Fowler-Nordheim tunneling, and channel hot electron injection, for example.
A memory cell or flash memory cell may be characterized in terms of its minimum feature size (F) and cell area (F
2
). For example, a standard NOR flash cell is typically quoted as a ten square feature cell and a standard NAND flash cell is approximately a 4.5 square feature cell. Typical DRAM (dynamic random access memory) cells are between 8 F
2
and 6 F
2
. Cell area (F
2
) is determined according to a well known methodology and represents the multiple of the number of features along the x and y dimensions of a memory cell. A suitable illustration of feature size is presented in U.S. Pat. No. 6,043,562, the disclosure of which is incorporated herein by reference.
Memory devices can be created using 2-dimensional structures or using 3-dimensional structures. The 2-dimensional structures are also referred to as planar structures. Generally, 3-dimensional structures yield smaller cell sizes than planar structures. SRAMs and DRAMs have been designed using 3-dimensional structures, however few flash memory cells are fabricated using 3-dimensional structures. Most flash memory cells are fabricated using planar structures. Some flash memory cells have been fabricated using 3-dimensional structures, but they are, generally, in the size range of 4.5 F
2
to 8 F
2
which are not significantly smaller than flash memory cells fabricated using planar structures.
Accordingly, there is a need for a 3-dimensional flash memory device having a cell area of reduced square feature size.
SUMMARY OF THE INVENTION
According to one embodiment of the invention, a memory cell is disclosed. The memory cell comprises a source, a vertical channel, a drain and a horizontal floating gate. The vertical channel is formed over the source. The drain is formed over the vertical channel. The horizontal floating gate is formed over at least a portion of the drain.
According to another embodiment of the invention, a memory cell is disclosed. The memory cell comprises a source, a vertical channel, a drain, a horizontal floating gate and a vertical select gate. The vertical channel is formed over the source. The drain is formed over the vertical channel. The horizontal floating gate is formed over at least a portion of the drain. The vertical select gate is formed perpendicular to the horizontal floating gate.
According to yet another embodiment of the invention, a memory cell is disclosed. The memory cell comprises a first transistor and a select transistor. The first transistor comprises a source, a drain and a gate. The select transistor is coupled to the first transistor and comprises a source, a drain and a gate. The gate of the select transistor is formed perpendicular to the gate of the first transistor.
According to yet another embodiment of the present invention, a memory device is disclosed. The memory device includes a first n-type layer, a p-type layer and a second n-type layer. The p-type layer is formed over the first n-type layer. The second n-type layer is formed over the p-type layer forming a vertical channel.
According to yet another embodiment of the invention, a memory device is disclosed. The memory device includes a horizontal first n-type layer, a p-type layer, a horizontal second n-type layer, a horizontal floating gate and a vertical select gate. The horizontal first n-type layer is formed over a substrate. The p-type layer is formed over the first n-type layer. The horizontal second n-type layer is formed over the p-type layer. The horizontal floating gate is formed over the substrate. The vertical select gate is formed over the substrate. The p-type layer formed a vertical channel. The first n-type layer forms a buried source and the second n-type layer forms a drain.
According to yet another embodiment of the invention, a memory device is disclosed. The memory device includes a buried source, a vertical channel, a drain, a floating gate and a select gate. The buried source is formed over a substrate. The vertical channel is formed over the buried source. The drain is formed over the vertical channel. The floating gate is formed over the substrate. The select gate is formed perpendicular to the floating gate in a trench formed in the substrate. The memory device has a square feature size of 2F
2
.
According to yet another embodiment of the invention, a memory device is disclosed. The memory device includes a substrate, a first n-type layer, a p-type layer, a second n-type layer, a floating gate, a trench and a select gate. The substrate has at least one semiconductor layer. The first n-type layer is formed over the substrate. The p-type layer is formed over the first n-type layer. The second n-type layer is formed over the p-type layer. The floating gate is formed over the substrate. The trench is formed in the substrate. The select gate is formed on a sidewall of the trench.
According to yet another embodiment of the invention, a memory device is disclosed. The memory device includes a first n-type layer, a p-type layer, a second n-type layer, a select trench, a vertical select gate, digitlines, a self aligned floating gate and wordlines. The p-type layer is formed over the n-type layer. The second n-type layer is formed in the p-type layer. The select trench is formed in the substrate. The vertical select gate is formed in the select trench. The digitlines are formed over the second n-type layer. The self aligned floating gate is formed over the n-type layer. The wordlines are formed over the substrate and the digitlines.
According to yet another embodiment of the invention, a memory device is disclosed. The memory device includes a first n-type layer, a p-type layer, a second n-type layer, a select trench, a tungsten layer, a spacer, a tunnel oxide layer, a polysilicon layer and an oxide layer. The first n-type layer is formed over a substrate. The p-type layer is formed over the n-type layer. The second n-type layer is formed over the p-type layer. The select trench is formed in the substrate. The vertical select gate is formed in the select trench. The tungsten layer is formed over at least a portion of the second n-type layer. The spacer is formed over the tungsten layer. The tunnel oxide layer is formed over at least a portion of the substrate. The polysilicon layer is formed on the tunnel oxide layer. The oxide layer is formed on the polysilicon layer.
According to yet another embodiment of the invention, a method of fabricating a memory device having a square feature size of 2F
2
is disclosed. A substrate is provided. A first n-type layer is formed over the substrate. A p-type layer is formed over th
Dinsmore & Shohl LLP
Flynn Nathan J.
Quinto Kevin
LandOfFree
2F2 memory device system does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with 2F2 memory device system, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and 2F2 memory device system will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3221551