Image analysis – Image compression or coding – Pyramid – hierarchy – or tree structure
Reexamination Certificate
2006-12-12
2006-12-12
Mancuso, Joseph (Department: 2624)
Image analysis
Image compression or coding
Pyramid, hierarchy, or tree structure
Reexamination Certificate
active
07149362
ABSTRACT:
Coding, transcoding and iterative filtering methods and apparatus are described wherein a 2D FIFO is used to implement CACLA processing, and wherein the processing methods are block-oriented. A block-by-block processed input image or input coded image, which is delayed in an arbitrary number of lines and columns, is provided such that the output image is produced in a block-by-block schedule at a reduced or minimal memory access and memory size cost. A 2D FIFO which is memory-efficient in image block coding and decoding applications is described. The 2D FIFO has an associated scheduling mechanism for enabling delay of a block-by-block coded input signal, such as an image, in an arbitrary number of lines and columns, such that the output image is produced in a block-by-block schedule.
REFERENCES:
patent: 5067023 (1991-11-01), Kim
patent: 6640015 (2003-10-01), Lafruit et al.
patent: 6681051 (2004-01-01), Hoppe et al.
patent: 6834123 (2004-12-01), Acharya et al.
patent: 2003/0108247 (2003-06-01), Acharya et al.
patent: 0 938 061 (1999-08-01), None
Lafruit et al, “Reduction of the memory requirements for the VLSI implementation of the fast wavelet transform, using a space filling curve”, Proceedings of the Third Int. conf. on Electronics, Circuits, and Systems, 1996, vol. 2, pp. 836-839.
Lafruit et al, “An Efficient VLSI Architecture for 2-D Wavelet Image Coding with Novel Image Scan”, IEEE Trans. on Very Large Scale Integration (VLSI) Systems, vol. 7, Issue 1, Mar. 1999 pp. 56-68.
Chrysafis et al, “Line-based, reduced memory, wavelet image compression”, IEEE Transactions on Image Processing vol. 9, Issue 3, Mar. 2000 pp. 378-389.
Schelkens et al, “Implementation of an integer wavelet Transform on a Parallel TI TMS320C40 Platform”, 1999 IEEE Workshop on Signal Processing Systems, Oct. 20-22, 1999 pp. 81-89.
Andreopoulos, et al., “A Local Wavelet Transform implementation versus an optimal Row-Column algorithm for the 2D multilevel decomposition”, IEEE, pp. 330-333, (2001).
Andreopoulos, et al., “A wavelet-tree image coding system with efficient memory utilization”, IEEE, pp. 1709-1712.
Andreopoulos, et al., “Analysis of Wavelet Transform Implementations For Image and Texture Coding Applications in Programmable Platforms”, IEEE, pp. 273-284, (2001).
Bao, et al., “Design of Wavelet-Based Image Codec in Memory-Constrained Environment,” IEEE Transactions on Circuits and Systems for Video Technology, vol. 11, No. 5, pp. 642-650, (May 2001).
Chang, et al., “A high speed VLSI architecture of discrete wavelet transform for MPEG-4”, IEEE Transactions On Consumer Electronics, vol. 43 No. 3, pp. 623-627, (Aug. 1997).
Chrysafis, et al., “Line-based, reduced memory, wavelet image compression”, IEEE Transactions On Image Processing, vol. 9, No. 3, pp. 378-389, (Mar. 2000).
Knowles, “VLSI architecture for the discrete wavelet transform”, Electronics-Letters, vol. 26, No. 15, pp. 1184-1185, (Jul. 19, 1990).
Lafruit, et al., “The Local Wavelet Transform: a memory-efficient, high-speed architecture optimized to a Region-Oriented Zero-Tree Coder”, Integrated Computer-Aided Engineering vol. 7, No. 2, pp. 89-103, (Mar. 2000).
Lafruit, et al., “Optimal Memory Organization for scalable texture codecs in MPEG-4” IEEE trans. on Circuits & Systems for Video technology vol. 9, No. 2, pp. 218-243, (Mar. 1999).
Lian, et al., “Lifting based discrete wavelet transform architecture for JPEG2000”, IEEE International symposium on Circuits and Systems, pp. 445-448, (2001).
Nibouche, et al., “Design and FPGA implementation of orthonormal discrete wavelet transforms”, IEEE, pp. 312-315, (2000).
Nibouche, et al., “Design and FPGA implementation of biorthogonal discrete wavelet transforms”, IEEE, pp. 103-106, (2001).
Nibouche, et al., “Rapid prototyping of orthonormal wavelet transforms on FPGA's”, IEEE, pp. 577-580, (2001).
Omaki, et al., “Realtime wavelet video coder based on reduced memory accessing”, IEEE, pp. 15-16, (2001).
Shapiro, “Embedded Image Coding using Zerotrees of Wavelet Coefficients,” IEEE Transactions on Signal Processing, vol. 41, No. 12, pp. 3445-3462, (Dec. 1993).
Sheu, et al., “A VLSI architecture design with lower hardware cost and less memory for separable 2-D discrete wavelet transform”, IEEE, pp. 457-460, (1998).
Simon, et al. “An ultra low-power adaptive wavelet video encoder with integrated memory”, IEEE Journal of Solid-State Circuits, vol. 35 No. 4, pp. 572-582, (Apr. 2000).
Singh, et al., “A distributed memory and control architecture for 2-D discrete wavelet transform”, IEEE, pp. 387-390 (1999).
Sweldens, “The Lifting Scheme: A New Philosophy in Biorthogonal Wavelet Constructions”, Proceedings of the SPIE vol. 2569, pp. 68-79, (1995).
Taubman, “High Performance Scalable Image Compression with EBCOT”, IEEE Transactions on Image Processing, vol. 9, No. 7, pp. 1158-1170, (Jul. 2000).
Vishwanath, et al., “VLSI Architectures for the Discrete Wavelet transform”, IEEE Transactions on Circuits and Systems-II: Analog and Digital Signal Processing, vol. 42, No. 5, pp. 305-316, (May 1995).
Bao Y. et al. “Design Of Wavelet-Based Image Codec In Memory-Constrained Environment” Ieee Transactions On Circuits And Systems For Video Technology, IEEE Inc. New York, US, vol. 11, No. 5, May 2001, pp. 642-650, XPOO1096943 ISSN: 1051-8215.
Lafruit G. et al. “Optimal Memory Organization For Scalable Texture Codecs In MPEG-4” IEEE Transactions On Circuits And Systems For Video Technology, IEEE Inc. New York, US vol. 9, No. 2, Mar. 1999, pp. 218-242, XP000805528 ISSN: 1051-8215.
Masoudnia A. et al. “A FIFO-based architecture for high speed image compression” 8th IEEE International Conference on Electronics, Circuits and Systems, 2001, vol. 1, Sep. 2, 2001, pp. 221-224, XP010562975.
Nachtergaele L. et al. “Implementation of a scalable MPEG-4 wavelet-based visual texture compression system” Design Automation Conference, 1999. Proceedings. 36th New Orleans, LA, USA Jun. 21-25, 1999, Piscataway, NJ, USA,IEEE, US, Jun. 21, 1999, pp. 333-336, XP010344003 ISBN: 1-58113-092-9.
Schelkens P. et al. “Efficient implementation of embedded zero-tree wavelet encoding” Electronics, Circuits and Systems, 1999. Proceedings of ICECS '99. The 6th IEEE International Conference on PAFOS, Cyprus Sep. 5-8, 1999, Piscataway, NJ, USA,IEEE, US vol. 2, Sep. 5, 1999, pp. 1155-1158, XP010361619 ISBN: 0-7803-5682-9.
Shapiro J. M. “Embedded Image Coding Using Zerotrees Of Wavelet Coefficients” IEEE Transactions On Signal Processing, IEEE, Inc. New York, US, vol. 41, No. 12, Dec. 1, 1993, pp. 3445-3462, XP000426658 ISSN: 1053-587X.
Lafruit Gauthier
Masschelein Bart
Ge Yuzhen
Interuniversitair Microelektronica Centrum (IMEC vzw)
Knobbe Martens Olson & Bear LLP
Mancuso Joseph
LandOfFree
2D FIFO device and method for use in block based coding... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with 2D FIFO device and method for use in block based coding..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and 2D FIFO device and method for use in block based coding... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3717856