Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reexamination Certificate
2002-06-26
2003-05-27
Ho, Hoai (Department: 2818)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
C257S315000, C438S257000, C365S185330
Reexamination Certificate
active
06570211
ABSTRACT:
TECHNICAL FIELD OF THE INVENTION
The present invention relates generally to semiconductor devices and more particularly to flash memory devices.
BACKGROUND OF THE INVENTION
There has long been a demand for small, portable personal devices. These devices include cellular phones, personal computing equipment, and personal sound systems, which are sought in continuously smaller sizes and with continuously lower power requirements. At the same time that smaller and more portable devices are sought, computational power and on-chip memory requirements are increasing. In light of these requirements, there has been a long-felt need for computational devices that have substantial memory and logic functions integrated within individual semiconductor chips. Preferably, the memory is configured such that if power is interrupted, as when a battery fails, the contents of the memory are retained. Memory that retains its content without a continuous supply of power is called non-volatile memory. Non-volatile memory types include, for example, electrically erasable, programmable read only memory (EEPPROM) and flash EEPROM.
The term “flash” refers to the ability of the memory to be erased in blocks. As in other non-volatile memory devices, flash memory devices typically store electrical charges, representing data, in transistors having either a floating-gate or a charge-trapping dielectric. The stored charges affect the threshold voltage of the transistors. For example, in an n-channel floating-gate transistor an accumulation of electrons in the floating-gate electrode creates a high threshold voltage in the transistor. The presence or absence of the stored charge can be determined by whether current flows between a source region and a drain region of the transistor when appropriate voltages are applied to the control gate, source, and drain.
Various structures have been proposed for making flash memory devices more compact. One such structure is a virtual ground array. While a non-virtual ground array structure has dedicated source and drain regions for reading and writing operations, a virtual ground array structure reduces the spacing between cells by employing dual purpose bit lines that can serve as either sources or drains according to the voltages applied.
Myriad other approaches have been proposed for making flash memory devices more compact. These approaches include improved processing techniques to produce smaller cells, improved materials that lend themselves to smaller cell sizes, and improved architectures that use space more efficiently. Nonetheless, there remains a long felt need for more compact flash memory devices.
SUMMARY OF THE INVENTION
The following presents a simplified summary of the invention in order to provide a basic understanding of some of its aspects. This summary is not an extensive overview of the invention and is intended neither to identify key or critical elements of the invention nor to delineate its scope. The primary purpose of this summary is to present some concepts of the invention in a simplified form as a prelude to the more detailed description that is presented later.
One aspect of the invention relates to a virtual ground array flash memory device in which individual combined source/drain regions are shared by more than two memory cells. For example, source/drain regions can be shared by four adjacent memory cells. Such sharing is possible, for example, through another aspect of the invention, wherein word lines are provided with dead end branches that extend to provide a second data adjacent to a memory cell that lies along the main branch of the word line, thereby providing multiple data bits per unit cell, for example a 2 bit/cell memory architecture.
A further aspect of the invention relates to a flash memory device wherein the memory cells are arrayed and a first portion of the memory cells are read with source and drain regions sharing a row of the array and a second portion of the memory cells are read with source and drain regions sharing a column of the array.
A still further aspect of the invention relates to a flash memory device wherein there are approximately two memory cells for each unit cell in the device. Where a memory can be divided into repeating units, a unit cell is the smallest repeating unit into which the memory can be divided. A memory cell includes a memory cell stack having a channel region isolated from the channel regions of adjacent stacks by source regions, drain regions, and/or isolation regions. The invention in its various aspects can provide flash memory devices that are more compact than conventional flash memory devices.
Yet another aspect of the present invention relates to a method of forming a flash memory device. The method comprises depositing and patterning a first polysilicon layer to form main branches of word lines, followed by the formation of an interpoly dielectric and a control gate layer. The interpoly dielectric and control gate layers are then patterned to form dead end branches associated with word lines which provide for a multiple bit per unit cell flash memory architecture.
In still another aspect of the present invention, a first polysilicon layer is formed and patterned, and an interpoly dielectric and second polysilicon layer forming a control gate layer are formed thereover. A hard mask is then formed and patterned, and sidewall spacers are then formed on the hard mask edges. The hard mask with sidewall spacers is then employed to pattern the word lines having dead branches associated therewith, wherein the sidewall spacer thickness dictates a distance between a dead end branch of one word line and a neighboring word line, and thus facilitates a close spacing between neighboring word lines, thereby improving cell density in the core region of the device.
Other advantages and novel features of the invention will become apparent from the following detailed description of the invention and the accompanying drawings. The detailed description of the invention and drawings provide exemplary embodiments of the invention. These exemplary embodiments are indicative of but a few of the various ways in which the principles of the invention can be employed.
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Fastow Richard
He Yue-song
Wei Zheng
Advanced Micro Devices , Inc.
Eschweiler & Associates LLC
Ho Hoai
Tran Long
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