2×VDD-tolerant logic circuits and a related...

Details 2×VDD-tolerant logic circuits and a related... 2×VDD-tolerant logic circuits and a related...

2011-03-29

2011-03-29

Tran, Anh Q (Department: 2819)

Electronic digital logic circuitry

Signal sensitivity or transmission integrity

Bus or line termination

C326S032000, C326S033000, C326S062000, C326S080000

Reexamination Certificate

active

07915914

ABSTRACT:
A 2×VDD-tolerant input/output (I/O) buffer circuit with process, voltage, and temperature (PVT) compensation suitable for CMOS technology is disclosed. A 2×VDD-tolerant I/O buffer with a PVT compensation circuit is implemented with novel 2×VDD-tolerant logic gates. Output slew rate variations can be kept within smaller ranges to match maximum and minimum timing specifications. A 2×VDD tolerant logic circuit for implementing the I/O buffer is also disclosed.

REFERENCES:
patent: 5498977 (1996-03-01), Pickup
patent: 7123066 (2006-10-01), Bazes
patent: 7449936 (2008-11-01), Shin et al.
patent: 7495465 (2009-02-01), Khan et al.
patent: 7579861 (2009-08-01), Shin et al.
Khan et al., “Techniques for On-Chip Process Voltage and Temperature Detection and Compensation,” Proceedings of the 19thInternational Conference on VLSI Design (VLSID '06), 1063-9667/06, 2006 IEEE.

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