2×VDD-tolerant logic circuits and a related...

Details 2×VDD-tolerant logic circuits and a related... 2×VDD-tolerant logic circuits and a related...

2011-04-26

2011-04-26

Tran, Anh Q (Department: 2819)

Electronic digital logic circuitry

Interface

Supply voltage level shifting

C326S068000, C326S080000

Reexamination Certificate

active

07932748

ABSTRACT:
A 2×VDD-tolerant input/output (I/O) buffer circuit with process, voltage, and temperature (PVT) compensation suitable for CMOS technology is disclosed. A 2×VDD-tolerant I/O buffer with a PVT compensation circuit is implemented with novel 2×VDD-tolerant logic gates. Output slew rate variations can be kept within smaller ranges to match maximum and minimum timing specifications. A 2×VDD tolerant logic circuit for implementing the I/O buffer is also disclosed.

REFERENCES:
patent: 7046036 (2006-05-01), Chen et al.
patent: 7123066 (2006-10-01), Bazes
patent: 7495465 (2009-02-01), Khan et al.
patent: 7579861 (2009-08-01), Shin et al.
patent: 2006/0091907 (2006-05-01), Khan
Khan et al., “Techniques for On-Chip Process Voltage and Temperature Detection and Compensation,” Proceedings of the 19thInternational Conference on VLSI Design (VLSID '06), 1063-9667/06, 2006 IEEE.

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