2-write 3-read SRAM design using a 12-T storage cell

Details 2-write 3-read SRAM design using a 12-T storage cell 2-write 3-read SRAM design using a 12-T storage cell

2007-12-06

2009-12-01

Auduong, Gene N. (Department: 2827)

Static information storage and retrieval

Systems using particular element

Flip-flop

C365S210130, C365S230050

Reexamination Certificate

active

07626854

ABSTRACT:
One embodiment of the present invention sets forth a twelve transistor static random access memory storage cell that provides two write ports and three read ports. The write word line operates at twice the clock frequency. The write bit lines are differential to provide high-performance writes. Each read word line operates at the clock frequency. Single-ended read bit lines are used to provide read performance comparable to write performance. The resulting storage cell only requires four horizontal word lines and five vertical bit lines, enabling very dense, yet high-performance designs.

REFERENCES:
patent: 5742557 (1998-04-01), Gibbins et al.
patent: 7304352 (2007-12-01), Muller et al.
patent: 7440356 (2008-10-01), Venkatraman et al.
patent: 2008/0155362 (2008-06-01), Chang et al.
patent: 2009/0016138 (2009-01-01), Bhatia

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