2-transistor floating-body dram

Details 2-transistor floating-body dram 2-transistor floating-body dram

2008-06-24

2008-06-24

Mai, Son L. (Department: 2827)

Static information storage and retrieval

Systems using particular element

Capacitors

C365S149000, C365S182000, C365S184000

Reexamination Certificate

active

07391640

ABSTRACT:
A dynamic random access memory includes a cell having a circuit between a floating-body transistor and a bit line. Activation of the circuit is controlled to provide isolation between the floating body and bit-line voltage both during write operations and during times when the cell is unselected. The added isolation improves performance, for example, by reducing the need for gate-to-body coupling and the magnitude of voltage swings between the bit lines.

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S. Tang et al., Floating-Body DRAM with Two-Phase Write for Low Voltage Operation, Intel Invention Disclosure #31978, Apr. 2003, 3 pages.

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