2-bit/cell type nonvolatile semiconductor memory

Static information storage and retrieval – Floating gate – Particular biasing

Reexamination Certificate

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C365S185280, C365S185260, C365S185010, C365S182000

Reexamination Certificate

active

06324099

ABSTRACT:

This application is based on Japanese Patent Application hei 11-334916, filed on Nov. 25, 1999, the entire contents of which are incorporated herein by reference.
BACKGROUND OF THE INVENTION
a) Field of the Invention
The present invention relates to a nonvolatile semiconductor memory and its control method, the memory storing data by capturing electric charges in an insulating film having a carrier trap layer.
b) Description of the Related Art
An insulated gate type field effect transistor has an insulated gate electrode on a gate insulating film formed on the surface of a channel region in a semiconductor substrate and a pair of source/drain regions formed in the semiconductor substrate on both sides of the gate electrode. An on/off state of the insulated gate type field effect transistor is determined by a voltage of the gate electrode relative to one of the source/drain regions.
A nonvolatile memory capable of changing its on/off state at the same gate voltage with a presence/absence of charge carriers in the gate insulating film can be realized by providing the gate insulating film with the structure capable of storing charge carriers. The charge carrier storage structure can be formed by a floating gate electrode and a silicon nitride film and the like. A dielectric carrier trap structure having a silicon nitride film sandwiched between silicon oxide films is known as an oxide-nitride-oxide (ONO) film.
A known method of writing/erasing charges in the nitride film of an ONO film is to apply a sufficiently high voltage across the gate electrode and channel region and to let charge carriers tunnel from the channel region into the nitride film, or in a reverse direction from the nitride film into the channel region.
A nonvolatile semiconductor memory having a p-type channel region, n-type source/drain regions, a gate insulating film with a carrier storage function, and a gate electrode on the gate insulating film will be described, the memory of this type being used only for illustrative purposes.
JP-B-5-326884 proposes a semiconductor memory. According to this memory, a p-type pocket layer surrounding an n-type drain region is formed. In writing data, hot electrons are injected into the nitride film by applying a high voltage (about 7 V) to the drain region and a write voltage to the gate electrode. In erasing data, an erase programming voltage is applied to the drain region to produce an interband tunneling effect near at the boundary between the drain region and pocket layer and inject some of hot holes into the nitride film.
U.S. Pat. No. 5,768,192 proposes a method of selectively injecting hot electrons either in one region or in the other region of a nitride film by flowing programming current between one (first region) of the source/drain regions and the other (second region) either in one direction or in the opposite direction.
If electrons are flowed from the first region to the second region, these electrons become hot electrons and injected into the nitride film near the second region. If electrons are flowed from the second region to the first region, these electrons become hot electrons and injected into the nitride film near the first region.
In the read process, read electron current flowed from the second region to the first region is influenced greatly by stored charges near at the second region but is influenced less by stored charges near at the first region. Read electron current flowed from the first region to the second region is influenced greatly by stored charges near at the first region but is influenced less by stored charges near at the second region.
Nonvolatile memories of a 2-bit/1-cell type have been proposed as described above. A memory cell of a 2-bit/1-cell type having the structure similar to a conventional memory cell can provide a twofold memory capacity.
U.S. Pat. No. 768,192 does not teach the erase method although it discloses the programming and the read method.
SUMMARY OF THE INVENTION
It is an object of the present invention to provide a nonvolatile semiconductor memory capable of storing a plurality of data per one cell, being manufactured with ease and having high reliability.
It is another object of the invention to provide a novel control method for a nonvolatile semiconductor memory capable of storing a plurality of data per one cell.
According to one aspect of the present invention, there is provided a nonvolatile semiconductor memory comprising: a semiconductor substrate of a first conductivity type; first and second diffusion regions of a second conductivity type symmetrically formed in a surface layer of the semiconductor substrate to define a channel region therebetween; a gate insulating film formed on the channel region, the gate insulating film including a carrier trap layer capable of trapping charge carriers; a gate electrode formed on the gate insulating film; and a control circuit for controlling: in a data write mode, to apply a high level voltage to the gate electrode, a low level voltage to one of the first and second diffusion regions, and a high level voltage to the other of the first and second diffusion regions to inject hot carriers of the second conductivity type in the carrier trap layer near the diffusion region applied with the high level voltage; in a data read mode, to flow carriers of the second conductivity type in the channel region along a direction opposite to a direction in the data write mode; and in a data erase mode, to apply a low level voltage or an opposite polarity voltage to the gate electrode, a low level voltage to one of the first and second diffusion regions, and a high level voltage to the other of the first and second diffusion regions to inject hot carriers of the first conductivity type generated by an interband tunneling effect near the other of the first and second diffusion regions, into the carrier trap layer near the diffusion region applied with the high level voltage, and neutralize charge carriers of the second conductive type.
According to another aspect of the present invention, there is provided a control method for a nonvolatile semiconductor memory having a number of nonvolatile semiconductor memory cells formed on a surface of a semiconductor substrate each having a gate insulating film including a carrier trap layer, a gate electrode formed on the gate insulating film, and first and second diffusion regions symmetrically formed in the semiconductor substrate on both sides of the gate electrode, the control method comprising the steps of: selectively writing data at a memory position near the first or second diffusion region through injection of hot carriers of a first conductivity type, by applying a first high level voltage to the first or second diffusion region, a second voltage lower than the first voltage to the second or first diffusion region, and a third voltage higher than the second voltage to the gate electrode; and selectively erasing the data at the memory position near the first or second diffusion region through injection of hot carriers of a second conductivity type opposite to the first conductivity type generated by an interband tunneling effect, by applying a first high level voltage to the first or second diffusion region, a second voltage lower than the first voltage to the second or first diffusion region, and a third voltage lower than the first voltage or of an opposite polarity to the gate electrode.
As above, a nonvolatile semiconductor memory is provided which is easy to be manufactured and has high reliability.
A semiconductor memory is provided which can store two bits per one cell, and be manufactured with ease and has high reliability.
A novel control method for such a nonvolatile semiconductor memory is also provided.


REFERENCES:
patent: 5768192 (1998-06-01), Eitan
patent: 6031763 (2000-02-01), Sansbury
patent: 5-326884 (1993-12-01), None

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