Electronic digital logic circuitry – Interface – Supply voltage level shifting
Reexamination Certificate
1999-06-02
2001-05-22
Nguyen, Viet Q. (Department: 2818)
Electronic digital logic circuitry
Interface
Supply voltage level shifting
C326S031000, C326S034000, C326S058000, C326S071000, C327S328000, C361S111000
Reexamination Certificate
active
06236236
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to input/output buffer circuits. In particular, the invention relates to input/output buffer circuits between a 2.5 volt circuit and a 3.3 or 5 volt circuit.
2. Description of the Related Art
The capability to support multiple power supplies (e.g., 5, 3.3, and 2.5 volts) and signaling specifications has been increasingly required for electronic interface circuits due to market need and process technology advancement. Because of design cycle reduction, development cycle reduction between different process technology generations, and the selection of different generation products from those available on the market to reduce the overall end-product cost, each new generation of interface circuit is desired to be able to work with the prior generation without causing any permanent damage or raising reliability concerns. This kind of device is called an over-voltage protection/tolerant interface circuit, an input/output (I/O) circuit, or a buffer circuit.
In the past, some over-voltage tolerant I/Os have been developed but they only work between two immediately successive generations of circuits. For example, many 3.3 volt powered I/O circuits are tolerant to the prior 5 volt generation. Many 2.5 volt powered I/O circuits are tolerant to 3.3 volt powered circuits. Thus for each generation, the common process technology may only support one prior generation of power supply.
One potential solution is to use a dual gate-oxide process. However, this may incur a higher cost and may be undesirable for most applications, in which lowering costs is often the driving design goal.
FIG. 1
shows a typical bi-directional I/O circuit without over-voltage tolerance circuits. Illustrated are an output enable signal node
40
, an output internal signal node
42
, an inverter
44
, a NAND gate
46
, a NOR gate
48
, a PMOS transistor
50
, an NMOS transistor
52
, an internal power supply node
54
, a ground node
56
, an external node
58
, a noninverting buffer
60
, and an input internal signal node
62
. When the output enable signal node
40
is high, the buffer circuit is output enabled and the signal at output internal signal node
42
can be sent to the external node
58
. When the output enable signal node
40
is low, the buffer circuit is output disabled and the external node
58
is in a high impedance state. If there is an incoming signal, it will be sent from the external node
58
to the input internal signal node
62
.
FIG. 2
shows an existing 3.3/5 volt tolerant I/O circuit that includes a floating N-well
80
, an output enable signal node
82
, an output internal signal node
84
, a NAND gate
86
, an inverter
88
, a NOR gate
90
, an internal power supply node
92
, a ground node
94
, an I/O power supply node
96
, an I/O ground node
98
, NMOS transistors
100
,
112
,
114
,
116
,
118
and
134
, PMOS transistors
102
,
104
,
106
,
108
,
110
and
138
, nodes
120
,
122
and
124
, an external node
128
, an inverter
136
, a noninverting buffer
130
, and an input internal signal node
132
. The floating N-well
80
connects to the bulk nodes of the transistors
102
,
104
,
106
,
108
and
110
that are exposed to 5 volts.
In the case of output disabled, nodes
120
and
122
are supposed to be high and low, respectively, to force transistors
106
and
118
into a high impedance state. If the external node
128
is driven from outside with 5 volts, transistor
116
protects the gate oxide of transistor
118
from the destructive 5 volts. On the other hand, node
120
is charged to 5 volts via transistor
108
and node
124
is charged to 5 volts via transistors
108
and
110
, turning off transistors
100
and
102
, so that the output of NAND gate
86
is isolated from the 5 volts on node
120
. In the meantime, the floating N-well
80
is charged to 5 volts minus V
diode
via various parasitic source or drain P/N junctions, where V
diode
is the voltage drop across these junctions. This ensures that the potential difference between any gate oxide of those transistors exposed to the 5 volts in the circuit is less than the allowable voltage.
In the case of output enabled, node
124
is charged to 0 volts via transistors
112
and
114
, so that the 5 volt tolerant circuits will not affect circuit performance in the normal output mode.
However, this 3.3/5 volt tolerant I/O circuit may not work when the process technology moves to a 2.5 volt power supply. Based on the JEDEC extended 5 volt signaling specifications (JESD12-6), the maximum voltage on the external node is 5.5 volts. From the 2.5 volt, 0.25 micron fabrication processes and related electrical specifications, the minimum power supply is 2.3 volts and the absolute maximum supply voltage (destructive) is 3.25 volts. That is, the voltage drop across any drain-gate, gate-source or gate-bulk of a transistor cannot exceed 3.25 volts. This may also be true for drain-bulk or source-bulk regions due to higher surface doping concentration and shallow source or drain P/N junctions for deep submicron CMOS technology.
Thus, when the circuit of
FIG. 2
is implemented at 0.25 micron fabrication process and powered by a 2.5 volt power supply, the biggest node-to-node voltage drop in the transistors, e.g., the drain-bulk voltage drop of transistor
116
, may not be tolerant to 5.5 volts.
SUMMARY OF THE INVENTION
The present invention addresses these and other problems of existing circuits with a 2.5 volt powered I/O circuit that is tolerant to both 3.3 and 5 volt circuits.
According to one embodiment, an apparatus according to one embodiment of the present invention includes a buffer circuit for communicating signals between an internal circuit having a low power supply voltage and an external circuit having a power supply voltage above that of the internal circuit. The apparatus includes a P-well control circuit and a number of NMOS transistors. The P-well control circuit is configured to receive a P-well control signal and an external signal, and in accordance therewith selectively generate a P-well voltage. The plurality of NMOS transistors is coupled to the P-well control circuit. At least one of the plurality of NMOS transistors has a bulk region configured to receive the P-well voltage. The plurality of NMOS transistors is further configured to receive the external signal having a first potential, and in accordance therewith selectively generate an internal signal having a second potential less than the first potential. The plurality of NMOS transistors is still further configured to receive the external signal having a third potential, and in accordance therewith selectively generate the internal signal having the second potential. The third potential is between the first potential and the second potential.
According to another embodiment, a method according to another embodiment of the present invention protects an internal circuit having a low power supply voltage from a signal communicated by an external circuit having a power supply voltage above that of the internal circuit. The method includes the steps of receiving an external signal having one of a first potential and a second potential; generating a P-well voltage corresponding to the external signal; providing the P-well voltage to a bulk region of at least one NMOS transistor; and generating an internal signal having a third potential and corresponding to the external signal. The third potential is less than the second potential, which is less than the first potential.
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Limbach & Limbach LLP
National Semiconductor Corporation
Nguyen Viet Q.
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