Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital data error correction
Patent
1998-10-23
2000-07-11
Moise, Emmanuel L.
Error detection/correction and fault detection/recovery
Pulse or data error handling
Digital data error correction
714792, 375262, 375265, H03M 1303, H04L 2302, H04L 512
Patent
active
06088827&
ABSTRACT:
A packetized trellis coder and method for providing error correction coding of IEEE 802.3 frame formatted Ethernet packets for transmission at one gigabit per second (Gbps) over twisted-pair wiring. The error correction code protects each byte of the ethernet frame with a parity bit constructed using a convolutional encoder such that a maximum likelihood sequence estimation at the receiver using a Viterbi decoder will result in a significant receiver performance gain. At the end of the Ethernet packet, the trellis coder restores the states of the convolutional encoder to a known value (state 0) before beginning Idle transmission so that the Viterbi decoder at the receiver can read off the end-of-packet symbols without any performance penalty. The mapping and the inverse mapping from raw data bits to symbols and vice-versa can be implemented with simple gates due to algorithmic symbol mapping of a 4-D trellis code via 1-D partitioning. The same redundancy that is needed for control code transmission in Ethernet frames is used to achieve the trellis coding and to improve receiver performance.
REFERENCES:
patent: 4622670 (1986-11-01), Martin
patent: 5497384 (1996-03-01), Fredrickson et al.
patent: 5548615 (1996-08-01), Wei
patent: 5559835 (1996-09-01), Betts
patent: 5699062 (1997-12-01), Widmer
Level One Communications Inc.
Moise Emmanuel L.
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