1-of-4 multiplier

Details 1-of-4 multiplier 1-of-4 multiplier

1998-11-05

2001-08-14

Malzahn, David H. (Department: 2121)

Electrical computers: arithmetic processing and calculating

Electrical digital calculating computer

Particular function performed

Reexamination Certificate

active

06275841

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to computer architecture, and more specifically to arithmetic operations with a digital computer.
2. Description of the Related Art
The speed of computer systems has exploded in recent years. Processor designs have become more efficient, and smaller substrate feature sizes and improved designs have allowed the achievement of speeds than had been thought impossible only a few years previously. However, the computer industry continues to drive toward even greater speeds in the future.
Early generations of logic circuit families of bipolar transistors, P-channel field effect transistors (PFETs or p-channel devices), and N-channel field effect transistors (NFETs or n-channel devices), have given way to processor designs using a logic circuit family known as CMOS (Complementary Metal Oxide Semiconductor). A traditional CMOS logicgate consists of a pair of complementary transistors where one transistor is a P-channel field effect transistor and the other transistor is a N-channel field effect transistor.
CMOS gained rapid favor for its ease of construction and simple design rules as well as its tolerance for noise and low power consumption. Power consumption in CMOS occurs only during the switching of the FETs. As a result of its wide popularity, most manufacturing capacity and design research investment in the last several years went into CMOS, which eventually overtook the other types of logic circuit families in nearly every category. Today, most people regard CMOS as the clear winner and preferred choice for virtually every semiconductor logic design task.
The advantage of the CMOS logic family, that it consumes power only when the FETs are switching, was limited to the older circuits that were slow by today's standards, and has become its primary disadvantage as clock rates have increased. The drive for faster dock rates means that the same CMOS circuit that used so little power in the past now requires ever increasing power. Typical CMOS processor designs have been known to consume power in the neighborhood of 50 watts or more. Such power demands (and their related heat dissipation problems) make designing computer systems very difficult.
Another logic family, non-inverting dynamic logic (also called domino logic, or asymmetrical CMOS), has lent itself to very high clock rates. Circuits within the nor-inverting dynamic logic have typically implemented each signal as a pair of wires or datapaths, providing all information in both true and complemented form. Twice as many wires or datapaths have been required as in a similar traditional CMOS design, because dynamic logic generally has not allowed inverted signals. Boolean AND, NAND, OR, NOR, and other well-known functions have been implemented in non-inverting dynamic logic using typical CMOS gates with nor-inverted signals. For example, U.S. Pat. No. 5,208,490 to Yetter et al and U.S. Pat. No. 5,640,108 to Miller describe methods for improving the speed and or accuracy (de-glitching) of dynamic logic circuits. However, the power consumption of the logic family remains problematic.
Synthesized multiplication implemented through repeated addition is extremely slow; for a 32-bit multiplication, 32 adds and 32 shifts would be required. Multicycle partial multipliers, which implement hardware to perform a portion of the multiplication (for example, 32 times 8 bits) in a single cycle, have improved multiplication latency dramatically, but typically have not been able to be pipelined, since all the hardware must be used in four successive cycles to produce a full product. Full multipliers, containing hardware sufficient to compute a full product (64 bits, following the 32-bit example), have been implemented to ii avoid recycling results, and consequently have improved multiplication throughput (that is, number of results produced per cycle), albeit atthe expense of additional hardware cost. The superior performance of full multipliers has made these devices a common implementation choice for contemporary microprocessors. The additional hardware cost of a full multiplier has been mitigated somewhat by shrinking device sizes and larger transistor budgets.
SUMMARY OF THE INVENTION
The present invention includes a family of N-NARY logic circuits, including a low-power high-speed full multiplier circuit that not only reduces the number of partial products through Booth encoding, but does so according to the number system in which the operands are encoded. Specifically, according to one aspect of the invention, the multiplier circuit receives operands encoded in a base-four numbering system and implements a radix-four Booth encoding. Moreover, the multiplier circuit is implemented using a new logic family, the N-NARY logic family, providing extremely fast calculations at very low power.
The present invention additionally comprises a method and apparatus for an integrated circuit (IC) that uses 1 of N signals to reduce both the circuit's power consumption and the circuit's wire-to-wire effective capacitance. Each of the 1 of N signals (also called “N-NARY signals”) of the N-NARY logic family of the present invention has a set of N wires or logic paths, of which at most one of the N logic paths belonging to each signal is active during an evaluation cycle. Various logic signals, including multiple signals of different widths, may be included within the N-NARY logic family. According toone aspect, the N-NARY logic family of the present invention implements a two bit logic circuit that uses “1 of 4” signals, each signal having a set of four wires (also called logic paths), of which one and only one of the four logic paths belonging to each signal is active during an evaluation cycle. Other embodiments of the present invention include the use of a 1 of 2 signal, a 1 of 3 signal, a 1 of 4 signal, and a 1 of 8 signal where one and only one of the wires of the signal is active. The “width” of the signals refers to the number of wires used to implement the signals, and may be regarded as a numerical base in a base-N numbering system. For example, 1 of 4 signals may be regarded as implementing numerical values in a base-four number system.
In addition to N-NARY signals, the N-NARY logic family of the present invention also includes N-NARY logic circuit designs. N-NARY logic circuits include a logic tree circuit that couples to various input logic paths and at least one set of output logic paths, which all use N-NARY signals, for example 1 of 4 signals. The logic tree circuit uses a single, shared logic tree with multiple evaluation paths for evaluating the function of the logic circuit.
According to one aspect, the device of the present invention further comprises a precharge circuit that precharges the transistors in the logic tree circuit and an evaluate circuit that controls the logic tree circuit's evaluation where both couple to the logic tree circuit. And finally, a clock signal couples to the precharge circuit and the evaluate circuit.
The present invention also includes an N-NARY logic approach to multiplication of numbers within a processor. According to one aspect, the present invention includes a multiplier comprising several radix4 Booth encoders, Booth multiplexers, and a Wallace tree of carry-save-adders implemented using N-NARY logic gates and N-NARY logic signals in a high-speed yet simple design.
The multiplier of the described embodiment implements a radix-4 Booth algorithm to encode the second (i.e., the multiplier) value. Conveniently, according to the exemplary aspect to the present invention, the radix of the Booth algorithm corresponds to the width of the signals used to implement the various numbers and values to be multiplied.
The step of multiplexing, however, is performed after a step of receiving an asserted evaluate signal. Prior to receiving the asserted evaluate signal, a step of providing a null output is substituted for the step of multiplexing. The step of providing a null output includes a step of configuring a c

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