0.7V two-port 6T SRAM memory cell structure with single-bit-line

Details 0.7V two-port 6T SRAM memory cell structure with single-bit-line 0.7V two-port 6T SRAM memory cell structure with single-bit-line

1999-10-27

2000-05-09

Le, Vu A.

Static information storage and retrieval

Systems using particular element

Flip-flop

365154, G11C 1100

Patent

active

060612681

ABSTRACT:
This invention discloses a novel low-voltage two-port 6T SRAM memory cell structure with single-bit-line simultaneous read-and-write access capability using partially-depleted SOI CMOS dynamic-threshold technique. With an innovative approach by connecting the body terminal of an NMOS device in the latch and the write access pass transistor to the write word line, this 6T memory cell can be used to provide SBLSRWA capability for 0.7 V two-port SOI CMOS VLSI SRAM as verified by MEDICI results.

REFERENCES:
patent: 5706226 (1998-01-01), Chan et al.
patent: 5774393 (1998-06-01), Kuriyama
patent: 5943528 (1999-08-01), Houston et al.

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