Result forwarding of either input operand to same operand...

Retiring early-completion instructions to improve computer...

Retiring instructions that meet the early-retirement...

Secondary reorder buffer microprocessor

Selected register decode values for pipeline stage register...

Selecting register or previous instruction result bypass as sour

Selectively powered retirement unit using a partitioned...

Simultaneously assigning corresponding entry in multiple...

Speculation pointers to identify data-speculative operations...

Stopping replay tornadoes

Storing results of producer instructions to facilitate...

Streaming vector processor with reconfigurable...

Superscalar microprocessor employing a future file for storing r

Superscalar processor with direct result bypass between...

System and method for eliminating write back to register...

System and method for eliminating write backs with buffer...

System and method for managing vertical dependencies in a...

System and method for retiring approximately simultaneously a gr

System and method for retiring approximately simultaneously...

System and method for retiring approximately simultaneously...