Separative extended gate field effect transistor based...
Series memory architecture
Series MOS ROM with tapered oxide side walls
Service programmable logic arrays with low tunnel barrier...
SEU hard majority voter for triple redundancy
SEU hard majority voter for triple redundancy
Shadow ram cell having a shallow trench eeprom
Shallow doped junctions with a variable profile gradation of...
Shallow doped junctions with a variable profile gradation of...
Shallow junction ferroelectric memory cell and method of making
Shallow junction ferroelectric memory cell having a laterally ex
Shallow junction formation
Shallow junction semiconductor
Shallow junction transistors which eliminating shorts due to...
Shallow source MOSFET
Shallow trench capacitor compatible with high-K / metal gate
Shallow trench isolation dummy pattern and layout method...
Shallow trench isolation formation
Shallow trench isolation formation
Shallow trench isolation on a silicon substrate using...